1. Introduction
2. Setting up
the environment
3. Starting Cadence
4. Library Manager
5. Creating new library
6. Creating new cell
7. Schematic Composer
8. Creating Symbols
9. Logic Simulation with
Verilog-XL
10. Custom layout with
Virtuoso
11. Layout Extraction
12. Layout Vs. Schematic (LVS)
13. Abstract view
Now we need to add cells to our library. We will show how to add a cell of a two input NAND gate.
In the Library Manager window, choose File -> New -> Cell View...
A window will pop up. For our NAND gate, we enter the following information
We have chosen to use "nand2x1" for the cell name of our SCL. The first value after the gate name is the number of inputs the gate has. The value after the "x" is the strength of the gate. For this NAND gate, we have two inputs with a strength of one.
Please also note that we first create schematic using Schematic Composer.
Click OK and the Virtuoso Schematic Editing window will then pop up.
