1. Introduction
2. Setting up
the environment
3. Starting Cadence
4. Library Manager
5. Creating new library
6. Creating new cell
7. Schematic Composer
8. Creating Symbols
9. Logic Simulation with
Verilog-XL
10. Custom layout with
Virtuoso
11. Layout Extraction
12. Layout Vs. Schematic (LVS)
13. Abstract view
First, in the Schematic View window, click Tools -> Simulation ->Verilog-XL, the Verilog simulation window will pop up as well as an initializing run directory window like below:
click OK
In the verilog simulation window, click Stimulus -> verilog... the following window will appear
click Yes
Then the next window will pop up
Choose testfixture.verilog and click OK
Now we have a verilog simulation file called testfixture.verilog. Open this file in nand2x1.run1 folder. It looks like this:
We will do some simple simulation on the NAND gate. Change the input at a different time as follows:
Save the file and quit.
Lets go back to the veilog simulation window in icfb. Click Simulation-> Start Interactive, simulation will now start.
After a while, when the text stops flowing, we can click Simulation -> Continue to finish up.
Make sure that there are no error messages in the log window.
After the simulation is done, we need to look at the waveforms. Click Debug->Utilities->View Waveform on your verilog simulation window.
The following window will appear:
In the new window, click Windows->Design Browser as shown above. Then the next window will appear:
Under "Instances in Current Context," click test as shown above and then A, B, Z (our input signal and output signal) as shown below. We can see that A, B, Z are added into the frame at the left.
Now you can click AddToWave and you will see the following waveforms:
After verifying the waveform, close the windows and let us go back to Library Manager.