1. Introduction
2. Setting up
the environment
3. Starting Cadence
4. Library Manager
5. Creating new library
6. Creating new cell
7. Schematic Composer
8. Creating Symbols
9. Logic Simulation with
Verilog-XL
10. Custom layout with
Virtuoso
11. Layout Extraction
12. Layout Vs. Schematic (LVS)
13. Abstract view
Layout is the most important part in creating a cell because all the future steps are derived from it.
First, we open the schematic window and click Tools -> Design Synthesis -> Layout XL.
a new window "Startup Option" pops up. Click OK
"Create New File" window pops up. Click OK again
Two windows will now be on your screen. One is
"LSW" and another "Layout Editing".
LSW is used when you need certain layers for your layout. the four buttons AV,
NV, AS, and NS stands for "all visible", "none visible",
"all select", and "none select". These buttons come in handy when you have multiple
layers at one point in your layout and you want to choose the lower layers.
You can get each instance one by one, but
we recommend you to generate them from the schematic. To do so, click Design ->
GenFromSource... a new window pops up.
We will create our own "Boundary" so you need to deselect it
in the "Layout Generation" section. Next
you need to change the Defaults' Layer/Master to metal1. Click "Apply
Pin Defaults" to set all the pins to metal1. Lastly, we want "Pin Label
Shape" to be Text Display so we know what pins they are. Click OK.
Your Layout should look something like this.
Next we want to get a template for this
cell.
In your Library Manager, click on Edit -> Library Path...
A new window will pop up. As you can see,
your SimpleSCL is in your library with its path attach to it. Now you need to add a
new library already created before by us. Type Template under the "Library"
column, and type the path /home/projects/abraham/vlsi464/Template under
the "Path". After you hit enter, you should see the link turn blue. If it is in
red, you have probably type the wrong path.
Now you need to save the "Library Path Editor" by File -> Save. You can
now close the window.
You should now see a new Library in your Library Manager. Let's open the layout by double clicking on it.
What is this? Well, it is the template
that we are going to follow. It is 7.2-micron in height. N-well covers half of
the template so one can place the PMOS in it. The grid-like boxes are
highlights, and the only purpose is to help the user line up the I/O pins. The
I/O pins have to be in the intersection of the grid for APR (automatic placement
and route, which we will cover in next sections).
N-tap and P-tap are already placed on the top and bottom, and it is where the
Vdd and Gnd rail will be located. Finally, the nselect and pselect box on the
left will be needed at the end when your layout is complete. The usage of the nselect
and pselect is to eliminate DRC (design rule check) when different cells are
being placed next to each other.
We want to copy the template to our
nand2x1 layout. But first we need to be able to select the highlights and
boundary lines on the template.
On your LSW window, click on Edit -> Set Valid Layers. You will see
the "Set
Valid Layer" window pop up.
Find hilite and prBound and
select them by clicking on the box on the right, like this:
.
Now click OK on "Set Valid Layer" and highlight the whole Template
layout. Go to Edit -> Copy, or type c. Click on anywhere that is
highlighted. Click on your nand2x1 layout and place the copied template
in it.
Now you can continue your layout.
First, you want to place the NMOS and PMOS on the template. Try to line them up
to save space.
Now you need to create a poly path to connect the poly on your transistors. Go
to LSW window and click on poly. Go back to layout window and Create
-> Path, or type p. draw the poly as the picture below.
If you mess up, you can hit u to undo or Edit -> Undo.
now with poly in place, we want to get the A and B pin in place. Since A and B pins are in metal1 layer, we want to create contact to connect poly to metal1 layer. Click on Create -> Contact... or o on keyboard. Follow the window below to add contact between M1_POLY.
Go back to your layout and place the contact in the intersections (since your pins needs to be in intersections) and try to place them in a different layer of your grid. Now you need to add the poly path to fill up the gap in between. Your contact should look something like below.
Now it is time to place the pins. We want to place the power nets first. Move your Vdd to the top and use Edit -> Stretch or simply s on the keyboard to expand the pin into a rail shown in the figure below. Now do the same thing for Gnd pin.
Now you need to route your metal1 to appropriate places. Lastly, you want to make a copy of the nselect and pselect boxes and place them at the edges of your design. Look at the picture below for reference. You also want to delete the extra taps and highlights. Then you need to resize the prBound (in purple)
If everything goes smoothly, your final layout for nand2x1 should look something like below.
Now it is time to do DRC (design rule check) Verify -> DRC. Click OK when the DRC window pops up.
Now go to your CIW window and make sure that you have no errors. If you have DRC error, you will find highlighted parallelogram showing where the problem is on your layout.