1. Introduction
2. Setting up
the environment
3. Starting Cadence
4. Library Manager
5. Creating new library
6. Creating new cell
7. Schematic Composer
8. Creating Symbols
9. Logic Simulation with
Verilog-XL
10. Custom layout with
Virtuoso
11. Layout Extraction
12. Layout Vs. Schematic (LVS)
13. Abstract view
In layout extraction, we want to get the parasitic capacitance value in our layout. To do so, in your layout window click on Verify -> Extract... the following window will pop up. Click on Set Switches in "Switch Names" and select Extract_parasitic_caps in the new selection window. Click OK and check to see if CIW gives any error.
If there are no errors, you should have an extracted view for your cell.
Double click on the extracted view. You should see a screen like this.
As you can see, the extract view calculates parasitic capacitance and places them on this view. Now we will check for LVS.