Cadence Design Environment

        1. Introduction
        2. Setting up the environment
        3. Starting Cadence
        4. Library Manager
        5. Creating new library
        6. Creating new cell
        7. Schematic Composer
        8. Creating Symbols
        9. Logic Simulation with Verilog-XL
        10. Custom layout with Virtuoso
        11. Layout Extraction
        12. Layout Vs. Schematic (LVS)
        13. Abstract view
 

 

 

LVS is a tool to check for differences in your layout and schematics.
First, open your layout extracted window and click Verify -> LVS...
A LVS window will appear. Fill out the form as the picture below.

Click Run in "LVS" window and wait for the result.
If you have not made any connection errors, you should have the following message
Click OK and exit the LVS if your check is successful

If the check is not successful, you need to click Error Display in the LVS window to see what part of your layout is not routed properly. Good Luck.

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