Automatic Place & Route

        1. mrgnet
        2. Library Verilog File
        3. LEF
        4. SiliconEnsemble(APR)
            a. Importing Files
            b. Initialize Floor Plan
            c. Place Pins
            d. Power Nets
            e. Cell Placement
            f. Filler Cell
            g. Routing
            h. Timing Report
            i. Export DEF format
        5. Custom IC design tools

Also make sure you have the Verilog file
        cp SC018.v simpleAPR/.

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