Automatic Place & Route

        1. mrgnet
        2. Library Verilog File
        3. LEF
        4. SiliconEnsemble(APR)
            a. Importing Files
            b. Initialize Floor Plan
            c. Place Pins
            d. Power Nets
            e. Cell Placement
            f. Filler Cell
            g. Routing
            h. Timing Report
            i. Export DEF format
        5. Custom IC design tools

We then will start the APR by typing

        seultra -m=36& (under APR directory)

Silicon ensemble will then start.  

Next-->