1. mrgnet
2.
Library Verilog File
3. LEF
4. SiliconEnsemble(APR)
a. Importing
Files
b. Initialize
Floor Plan
c. Place Pins
d. Power Nets
e. Cell
Placement
f. Filler
Cell
g. Routing
h. Timing
Report
i. Export DEF
format
5. Custom IC design tools
For the purpose of post parasitic extraction timing analysis, we need a timing report form APR. Click Report -> RC...
Click on DSPF and enter the name of the file. Also make sure that Extraction Model is PP.
Click OK