1. mrgnet
2.
Library Verilog File
3. LEF
4. SiliconEnsemble(APR)
a. Importing
Files
b. Initialize
Floor Plan
c. Place Pins
d. Power Nets
e. Cell
Placement
f. Filler
Cell
g. Routing
h. Timing
Report
i. Export DEF
format
5. Custom IC design tools
In the icfb, we can look at the result of the APR and then change the view into the layout view. The abstract view we created in icfb in the layout step is useful here.
Go back to standardcell directory
cd ~/standardcell
icfb&
Then we need to import the DEF file. Remember when we created the design in icfb, we created a SimpleDesign library. We can import to this library directly.
Click in CIW window File -> Import -> DEF... Enter the following information. Remember we need to give the full path of the DEF file.
In Library Manager, we can open autorouted view to see the result, it is as follows:
Click Design -> Save
Click Tools -> Layout. About the same window appears, but the tool bar changes.
Let us get the layout view.
Click Edit -> Search...
Click Add Criteria, Change Cell Name to View Name, enter abstract in the window next to it. ,
Click Replace, change Cell Name to View Name, enter layout.
It looks like this.
Click Apply and then Replace All. Close the window and the layout editor looks like this
A closer look.
If we have filler cells, the filler cells will fill in the gaps of the disconnections between the cells. Since we don't have the fillers, we need to extend our power wire and ground wires and extend our wells.
Now let's do a DRC check. Here is the log window after the DRC check.
There are three errors associated with the input and output pin at the boundary. As for the DRC check for the cells placement and routing, there are no errors.