1. mrgnet
2.
Library Verilog File
3. LEF
4. SiliconEnsemble(APR)
a. Importing
Files
b. Initialize
Floor Plan
c. Place Pins
d. Power Nets
e. Cell
Placement
f. Filler
Cell
g. Routing
h. Timing
Report
i. Export DEF
format
5. Custom IC design tools
For APR, we should first import the LEF file.
Click File -> Import -> LEF.... Choose our LEF file and then click OK.
Without any error, it should look like this:
Then we need to import our design.v and SC018.v Click File -> Import -> Verilog...
In the import Verilog Window, click Browse... Then another window will pop up. Click on SC018.v and then click Add
Click OK and follow the same procedure to add design.v
Next, in the Verilog Top Module, enter design.
Click OK. Make sure there is no error message in the log window and we can then proceed.