1. mrgnet
2.
Library Verilog File
3. LEF
4. SiliconEnsemble(APR)
a. Importing
Files
b. Initialize
Floor Plan
c. Place Pins
d. Power Nets
e. Cell
Placement
f. Filler
Cell
g. Routing
h. Timing
Report
i. Export DEF
format
5. Custom IC design tools
Click Route -> Plan Power...
A tool bar will pop up. Click on Add rings...
Fill in the information as below:
Click OK. Window will become like this
Close the tool bar and then let us proceed.