Automatic Place & Route

        1. mrgnet
        2. Library Verilog File
        3. LEF
        4. SiliconEnsemble(APR)
            a. Importing Files
            b. Initialize Floor Plan
            c. Place Pins
            d. Power Nets
            e. Cell Placement
            f. Filler Cell
            g. Routing
            h. Timing Report
            i. Export DEF format
        5. Custom IC design tools

Next we need to export the APR result back into icfb and look at the layout of the whole design.  First we need to export the abstract view of the design into DEF global format. Click File -> Export...

Make sure All is chosen and click OK.

We can now close the APR.

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