Automatic Place & Route

        1. mrgnet
        2. Library Verilog File
        3. LEF
        4. SiliconEnsemble(APR)
            a. Importing Files
            b. Initialize Floor Plan
            c. Place Pins
            d. Power Nets
            e. Cell Placement
            f. Filler Cell
            g. Routing
            h. Timing Report
            i. Export DEF format
        5. Custom IC design tools

Now you also need the LEF file from abstract generator
        cp abstract/run/SimpleSCL.lef simpleAPR/SimpleSCL.lef

Now you need to go into the folder
        cd simpleAPR
It is recommended to make a copy of the file you just made.
        mkdir APR
   cp *.* APR/
   cd APR

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