1. mrgnet
2.
Library Verilog File
3. LEF
4. SiliconEnsemble(APR)
a. Importing
Files
b. Initialize
Floor Plan
c. Place Pins
d. Power Nets
e. Cell
Placement
f. Filler
Cell
g. Routing
h. Timing
Report
i. Export DEF
format
5. Custom IC design tools
Click Floorplan -> Initialize Floorplan... following window will pop up
Click on Fixed Size and enter 50 in both Height and Width
Enter 20 for both Left/Right and Top/Bottom in IO to Core Distance
Click on Flip Every Other Row and Abut Rows
Click Calculate and the calculation of the area utilization is shown
Click OK and then the following will be shown
