1. mrgnet
2.
Library Verilog File
3. LEF
4. SiliconEnsemble(APR)
a. Importing
Files
b. Initialize
Floor Plan
c. Place Pins
d. Power Nets
e. Cell
Placement
f. Filler
Cell
g. Routing
h. Timing
Report
i. Export DEF
format
5. Custom IC design tools
Click Place -> Cells...
Click OK. The window will look like this.
