1. mrgnet
2.
Library Verilog File
3. LEF
4. SiliconEnsemble(APR)
a. Importing
Files
b. Initialize
Floor Plan
c. Place Pins
d. Power Nets
e. Cell
Placement
f. Filler
Cell
g. Routing
h. Timing
Report
i. Export DEF
format
5. Custom IC design tools
Filler cells are used for connecting the gaps between the cells after placement. If you have filler cells in the library, the next step is to add the filler cells. We do not have a filler cell in our library, but we put it here for your reference.
Click Place -> Filler Cells -> Add Cells...
If you do have a filler cell in your library, you may name it any name as long as the names match in model and prefix.