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Disclaimer: Many papers below have been made available in PDF format for easy access. However, please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.
Jump to -    Books/Books Chapters     Conference Papers     Journal Articles      Patents

BOOKS / BOOK CHAPTERS (Go to Top)

[B7] Bei Yu and David Z. Pan, "Design for Manufacturability with Advanced Lithography, " Springer, 2016 Edition

[B6] Bei Yu and David Z. Pan, "Layout Decomposition for Triple Patterning" in Encyclopedia of Algorithms (edited by M.-Y. Kao eds.), Springer, 2015 Edition

[B5] Minsik Cho and David Z. Pan, "Global Routing" in Encyclopedia of Algorithms (edited by M.-Y. Kao eds.), Springer, 2015 Edition

[B4] D. Z. Pan and M. Stan, "Physical Design and Interaction with Technology" in CAD Algorithms, Methods and Tools For Low-Power Circuits and Systems (edited by Enrico Macii), Jan. 2006 (IEEE Technology Survey)

[B3] D. Z. Pan, B. Halpin, and H. Ren, "Timing-Driven Placement" in Handbook of Algorithms for VLSI Physical Automation (edited by Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar), CRC Press, 2007 (Invited) (Amazon) (ISBN: 0849372429)

[B2] T. Luo and D. Z. Pan, "DPlace: Anchor Cell based Quadratic Placement with Linear Objective" in Modern Circuit Placement: Best Practices and Results (edited by Gi-Joon Nam and Jason Cong), Springer, 2007 (Invited) (Amazon) (ISBN: 038736837X)

[B1] M. Cho, J. Mitra, and D. Z. Pan, "Manufacturability Aware Routing" in Handbook of Algorithms for VLSI Physical Automation (edited by Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar), CRC Press, 2007 (Invited) (Amazon) (ISBN: 0849372429)


CONFERENCE PAPERS (Go to Top)

[C226] Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan and Ulf Schlichtmann, "TimingCamouflage: Improving Circuit Security against Counterfeiting by Unconventional Timing, " IEEE/ACM Design, Automation & Test in Europe (DATE), Dresden, Germany, March 2018. (accepted)

[C225] Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, and David Z. Pan, "Layout-Dependent Aging Mitigation for Critical Path Timing, " Asia and South Pacific Design Automation Conference (ASPDAC), Jeju, Korea, Jan. 22-25, 2018. (accepted)

[C224] Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, and David Z. Pan, "A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion, " Asia and South Pacific Design Automation Conference (ASPDAC), Jeju, Korea, Jan. 22-25, 2018. (accepted)

[C223] Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, and David Z. Pan, "Logic Synthesis for Energy-Efficient Photonic Integrated Circuits, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Jeju, Korea, Jan. 22-25, 2018. (accepted)

[C222] Zheng Wang, Zhoufeng Ying, Shounak Dhar, Zheng Zhao, David Z. Pan, and Ray T. Chen, "Optical switches based carry-ripple adder for future high-speed and low-power consumption optical computing, " In CLEO: Science and Innovations, pp. STh1N-2. Optical Society of America, 2017.

[C221] Zhoufeng Ying, Zheng Wang, Shounak Dhar, Zheng Zhao, David Z. Pan, and Ray T. Chen, "On-chip Microring Resonator Based Electro-optic Full Adder for Optical Computing, " In CLEO: QELS_Fundamental Science, pp. JW2A-147. Optical Society of America, 2017.

[C220] Zheng Wang, Zhoufeng Ying, Shounak Dhar, Zheng Zhao, David Pan, and Ray T. Chen, "Nanophotonic devices for power-efficient computing and optical interconnects, " In Photonics Society Summer Topical Meeting Series (SUM), 2017 IEEE, pp. 7-8. IEEE, 2017. (Invited Paper)

[C219] Wuxi Li, Meng Li, Jiajun Wang, and David Z. Pan, "UTPlaceF 3.0: A Parallelization Framework for Modern FPGA Global Placement, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Irvine, CA, Nov. 13-16, 2017. (Invited Paper)

[C218] Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, and David Z. Pan, "DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node, " IEEE International Conference on Computer Design (ICCD), Boston, MA, Nov. 5-8, 2017. (accepted)

[C217] Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-han Kim, Praveen Raghavan, and David Z. Pan, "Patterning Aware Design Optimization of Selective Etching in N5 and Beyond, " IEEE International Conference on Computer Design (ICCD), Boston, MA, Nov. 5-8, 2017. (accepted)

[C216] Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, and David Z. Pan, "Computation on Silicon-on-Insulator-Based Photonic Integrated Circuits, " IEEE International Conference on ASIC (ASICON), Guiyang, China, Oct. 25-28, 2017. (Invited Paper)

[C215] Yibo Lin, Xiaoqing Xu, Jiaojiao Ou and David Z Pan, "Machine learning for mask/wafer hotspot detection and mask synthesis, " Photomask Technology, Oct 16, 2017. (Invited Paper)

[C214] Wei Ye, Yibo Lin, Xiaoqing Xu, Wuxi Li, Yiwei Fu, Yongsheng Sun, Canhui Zhan and David Z. Pan, "Placement Mitigation Techniques for Power Grid Electromigration, " IEEE International Symposium on Low Power Electronics and Design (ISLPED), Taipei, Jul. 24-26, 2017.

[C213] Xiaoqing Xu, Yibo Lin, Vinicius Livramento, and David Z. Pan, "Concurrent Pin Access Optimization for Unidirectional Routing, " ACM/IEEE Design Automation Conference (DAC), Austin, TX, Jun. 18-22, 2017.

[C212] Biying Xu, Shaolan Li, Nan Sun, and David Z. Pan, "A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology, " ACM/IEEE Design Automation Conference (DAC), Austin, TX, Jun. 18-22, 2017.

[C211] Derong Liu, Vinicius Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, and David Z. Pan, "Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups, " ACM/IEEE Design Automation Conference (DAC), Austin, TX, Jun. 18-22, 2017.

[C210] Meng Li, Liangzhen Lai, Vikas Chandra, and David Z. Pan, "Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack, " ACM/IEEE Design Automation Conference (DAC), Austin, TX, Jun. 18-22, 2017.

[C209] Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, and Yier Jin, "AppSAT: Approximately Deobfuscating Integrated Circuits, " IEEE International Symposium on Hardware Oriented Security and Trust (HOST), McLean, VA, USA, May 1-4, 2017. (Best Paper Award)

[C208] Travis Meade, Zheng Zhao, Shaojie Zhang, David Z. Pan, and Yier Jin, "Revisit Sequential Logic Obfuscation: Attacks and Defenses, " IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, May 28-31, 2017 (Invited Paper)

[C207] Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin and David Z. Pan, "DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment, " ACM International Symposium on Physical Design (ISPD), Portland, OR, Mar. 19-22, 2017.

[C206] Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun and David Z. Pan, "Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits, " ACM International Symposium on Physical Design (ISPD), Portland, OR, Mar. 19-22, 2017.

[C205] Shounak Dhar, Mahesh Iyer, Saurabh Adya, Love Singhal, Nikolay Rubanov and David Pan, "An Effective Timing-Driven Detailed Placement Algorithm for FPGAs, " ACM International Symposium on Physical Design (ISPD), Portland, OR, Mar. 19-22, 2017.

[C204] Joydeep Mitra, Andres Torres, and David Z. Pan, "Process, Design Rule, and Layout Co-optimization for DSA Based Patterning of Sub-10nm Finfet Devices, " SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 26 - Mar. 2, 2017

[C203] Joydeep Mitra, Andres Torres, and David Z. Pan, "Model Based Guiding Pattern Synthesis for On-target and Robust Assembly of Via and Contact layers using DSA, " SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 26 - Mar. 2, 2017.

[C202] Taiki Kimura, Tetsuaki Matsunawa, Chikaaki Kodama, Shigeki Nojima and David Z. Pan, "SOCS-based post-layout optimization for multiple patterns with light interference prediction, " SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 26 - Mar. 2, 2017.

[C201] Jiaojiao Ou, Brian Cline, Greg Yeric and David Z. Pan, "Efficient DSA and DP Hybrid Lithography Conflict Detection and Guiding Template Assignment, " SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 26 - Mar. 2, 2017.

[C200] Travis Meade, Shaojie Zhang, Zheng Zhao, David Z. Pan, and Yier Jin, "Gate-Level Netlist Reverse Engineering Tool Set for Functionality Recovery and Malicious Logic Detection, " International Symposium for Testing and Failure Analysis (ISTFA), Fort Worth, Texas, USA, Nov. 6-10, 2016.

[C199] Wuxi Li, Shounak Dhar, and David Z. Pan, "UTPlaceF: A Routability-Driven FPGA Placer with Physical and Congestion Aware Packing, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov. 7-10, 2016. (Invited Paper; 1st Place Winner of ISPD'16 Contest)

[C198] Yudong Tao, Changhao Yan, Yibo Lin, Shengguo Wang, David Z. Pan, and Xuan Zeng, "A Novel Unified Dummy Fill Insertion Framework with SQP-Based Optimization Method, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov. 7-10, 2016.

[C197] Shounak Dhar, Saurabh Adya, Love Singhal, Mahesh A. Iyer and David Z. Pan, "Detailed Placement for Modern FPGAs using 2D Dynamic Programming, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov. 7-10, 2016.

[C196] Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin and David Z. Pan, "Provably Secure Camouflaging Strategy for IC Protection, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov. 7-10, 2016.

[C195] Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert and David Z. Pan, "MrDP: Multiple-row Detailed Placement of Heterogeneous-sized Cells for Advanced Nodes, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov. 7-10, 2016.

[C194] Yibo Lin, Bei Yu, and David Z. Pan, "Detailed Placement In Advanced Technology Nodes: A Survey, " EEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Hangzhou, China, October 25-28, 2016. (Invited Paper)

[C193] Derong Liu, Bei Yu, Salim Chowdhury, and David Z. Pan, "Incremental Layer Assignment for Critical Path Timing, " ACM/IEEE Design Automation Conference (DAC), 2016.

[C192] Meng Li, Jin Miao, Kai Zhong, and David Z. Pan, "Practical Public PUF Enabled by Solving Max-Flow Problem on Chip, " ACM/IEEE Design Automation Conference (DAC), 2016.

[C191] Xiaoqing Xu, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, and David Z. Pan, "A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation, " ACM International Symposium on Physical Design (ISPD), Santa Rosa, CA, April 3-6, 2016.

[C190] Jiaojiao Ou, Bei Yu, and David Z. Pan, "Concurrent Guiding Template Assignment and Redundant Via Insertion for DSA-MP Hybrid Lithography, " ACM International Symposium on Physical Design (ISPD), Santa Rosa, CA, April 3-6, 2016.

[C189] Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, and David Z. Pan, "Hybrid Hotspot Detection using Regression Model and SOCS Kernels, " SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 21-25, 2016.

[C188] Yibo Lin, Xiaoqing Xu, Bei Yu, Ross Baldick, and David Z. Pan, "Triple/Quadruple Patterning Layout Decomposition via Novel Linear Programming and Iterative Rounding, " SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 21-25, 2016. (Best Student Paper Award)

[C187] Xiaoqing Xu, Brian Cline, Greg Yeric, and David Z. Pan, "Standard Cell Pin Access and Physical Design in Advanced Lithography, " SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 21-25, 2016. (Invited Paper)

[C186] Tetsuaki Matsunawa, Bei Yu, and David Z. Pan, "Laplacian Eigenmaps and Bayesian Clustering Based Layout Pattern Sampling and Its Applications to Hotspot Detection and OPC, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Macau, Jan. 25-28, 2016.

[C185] Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert and David Z. Pan, "Stitch Aware Detailed Placement for Multiple E-Beam Lithography, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Macau, Jan. 25-28, 2016.

[C184] Pengpeng Ren, Xiaoqing Xu, Peng Hao, Junyao Wang, Runsheng Wang, Ming Li, Jianping Wang, Weihai Bu, Jingang Wu, Walsum Wong, Shaofeng Yu, Hanming Wu, Shiuh-Wuu Lee, David Z. Pan, and Ru Huang, "Adding the Missing Time-Dependent Layout Dependency into Device-Circuit-Layout Co-Optimization -- New Findings on the Layout Dependent Aging Effects, " IEEE International Electron Devices Meeting (IEDM), 2015.

[C183] Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan and Gabriel Robins, "Toward Metrics of Design Automation Research Impact, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, November 2-6, 2015. (Invited Paper)

[C182] Bei Yu, Derong Liu, Salim Chowdhury and David Z. Pan, "TILA: Timing-Driven Incremental Layer Assignment, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, November 2-6, 2015.

[C181] Yibo Lin, Bei Yu, Biying Xu and David Z. Pan, "Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, November 2-6, 2015.

[C180] Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan and Deming Chen, "CSL: Coordinated and Scalable Logic Synthesis Techniques for Effective NBTI Reduction, " IEEE International Conference on Computer Design (ICCD), NY, Oct 18-21, 2015.

[C179] David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin, "Pushing Multiple Patterning in Sub-10nm: Are We Ready?, " ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015. (Invited Paper)

[C178] Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, and David Z. Pan, "PARR: Pin Access Planning and Regular Routing for Self-Aligned Double Patterning, " ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015.

[C177] Yibo Lin, Bei Yu, and David Z. Pan, "High Performance Dummy Fill Insertion with Coupling and Uniformity Constraints, " ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015.

[C176] Subhendu Roy, Derong Liu, Junhyung Um, and David Z. Pan, "OSFA: A New Paradigm of Gate Sizing for Power/Performance Optimizations under Multiple Operating Conditions, " ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015.

[C175] Keith Campbell, Pranay Vissa, David Z. Pan, and Deming Chen, "High-Level Synthesis of Error Detecting Cores through Low-Cost Modulo-3 Shadow Datapaths, " ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015.

[C174] Wei Ye, Bei Yu, Yong-Chan Ban, Lars Liebmann, and David Z. Pan, "Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line, " ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, PA, May 20-22, 2015.

[C173] Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, Moshe Preil, Azat Latypov, and David Z Pan, "Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design, " ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, PA, May 20-22, 2015.

[C172] Subhendu Roy, Pavlos M Mattheakis, Peter S Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet and David Z Pan, "Skew Bounded Buffer Tree Resynthesis for Clock Power Optimization, " ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, PA, May 20-22, 2015.

[C171] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, and David Z. Pan, "A Systematic Framework for Evaluating Standard Cell Middle-of-Line (MOL) Robustness for Multiple Patterning, " SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability IX, San Jose, CA, Feb. 23-27, 2015.

[C170] Tetsuaki Matsunawa, Jhih-Rong Gao, Bei Yu, and David Z. Pan, "A New Lithography Hotspot Detection Framework Based on AdaBoost Classifier and Simplified Feature Extraction, " SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability IX, San Jose, CA, Feb. 23-27, 2015.

[C169] Tetsuaki Matsunawa, Bei Yu, and David Z. Pan, "Optical proximity correction with hierarchical Bayes model, " SPIE Intl. Symp. Advanced Lithography - Optical Microlithography XXVIII, San Jose, CA, Feb. 23-27, 2015.

[C168] Bei Yu, David Z. Pan, Tetsuaki Matsunawa, and Xuan Zeng, "Machine Learning and Pattern Matching in Physical Design, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 19-22, 2015. (Invited Paper)

[C167] Jiwoo Pak, Bei Yu, and David Z. Pan, "Electromigration-aware Redundant Via Insertion, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 19-22, 2015.

[C166] Subhendu Roy, Mihir Choudhury, Ruchir Puri, and David Z. Pan, "Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 19-22, 2015.

[C165] Subhendu Roy, Pavlos Matthaiakis, Pavlos, Laurent Masse-Navette, and David Z. Pan, "Evolving Challenges and Techniques for Nanometer SoC Clock Network Synthesis, " IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, China, October 28-31, 2014. (Invited Paper)

[C164] Bei Yu, Gilda Garreton, and David Z. Pan, "Layout Compliance for Triple Patterning Lithography: an Iterative Approach, " SPIE/BACUS Photomask Symposium, Monterey, CA, September 2014. (Invited Paper)

[C163] Jhih-Rong Gao, Xiaoqing Xu, Bei Yu, and David Z. Pan, "MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction, " ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 1-5, 2014.

[C162] Bei Yu and David Z. Pan, "Layout Decomposition for Quadruple Patterning Lithography and Beyond, " ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 1-5, 2014.

[C161] Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Through-Silicon-Via Material Property Variation Impact on Full-Chip Reliability and Timing, " IEEE International Interconnect Technology Conference (IITC), San Jose, CA, May 20-23, 2014.

[C160] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu and David Z. Pan, "Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization, " ACM International Symposium on Physical Design (ISPD), Petaluma, CA, March 2014.

[C159] Yilin Zhang and David Z. Pan, "Timing-Driven, Over-the-Block Rectilinear Steiner Tree Construction with Pre-Buffering and Slew Constraints, " ACM International Symposium on Physical Design (ISPD), Petaluma, CA, March 2014.

[C158] Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, and David. Z. Pan, "Clock Tree Resynthesis for Multi-corner Multi-mode Timing Closure, " ACM International Symposium on Physical Design (ISPD), Petaluma, CA, March 2014. (Best Paper Award)

[C157] Bei Yu, Jhih-Rong Gao, Xiaoqing Xu, and David Z. Pan, "Bridging the Gap from Mask to Physical Design for Multiple Patterning Lithography, " SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability VIII, San Jose, CA, Feb. 23-27, 2014. (Invited Paper)

[C156] Jhih-Rong Gao, Bei Yu, and David Z. Pan, "Accurate Lithography Hotspot Detection Based on PCA-SVM Classifier with Hierarchical Data Clustering, " SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability VIII, San Jose, CA, Feb. 23-27, 2014.

[C155] Jhih-Rong Gao, Bei Yu, David Z. Pan, "Self-aligned Double Patterning Layout Decomposition with Complementary E-Beam Lithography, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Singapore, Jan. 20-23, 2014

[C154] Yilin Zhang, Salim Chowdhury, David Z. Pan, "BOB-Router: A New Buffering-Aware Global Router with Over-the-Block Routing Resources Optimization, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Singapore, Jan. 20-23, 2014

[C153] Subhendu Roy and David Z. Pan, "Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown, " IEEE/ACM International Conference on VLSI Design (VLSID), Mumbai, India, Jan. 5-9, 2014

[C152] Jiwoo Pak, Sung Kyu Lim and David Z. Pan, "Electromigration Study for Multi-scale Power/Ground Vias in TSV-based 3D ICs, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 18-21, 2013.

[C151] Bei Yu, Xiaoqing Xu, Jhih-Rong Gao and David Z. Pan, "Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 18-21, 2013. (William J. McCalla Best Paper Award)

[C150] Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas and David Z. Pan, "A High-Performance Triple Patterning Layout Decomposer with Balanced Density, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 18-21, 2013.

[C149] Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert and David Z. Pan, "Clock Power Minimization using Structured Latch Templates and Decision Tree Induction, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 18-21, 2013.

[C148] Jhih-Rong Gao, Bei Yu, Duo Ding, and David Z. Pan, "Lithography Hotspot Detection and Mitigation in Nanometer VLSI, " IEEE International Conference on ASIC (ASICON) , Shenzhen, China, Oct. 28-31, 2013. (Invited Paper)

[C147] Subhendu Roy, Mihir Choudhury, Ruchir Puri, and David Z. Pan, "Towards Optimal Performance-Area Trade-off in Adders by Synthesis of Parallel Prefix Structures, " ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2-6, 2013.

[C146] Yang Li and David Z. Pan, "An Accurate Semi-Analytical Framework for Full-Chip TSV-induced Stress Modeling, " ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2-6, 2013.

[C145] Bei Yu, Kun Yuan, Jhih-Rong Gao, and David Z. Pan, "E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System, " ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2-6, 2013.

[C144] Bei Yu, Jhih-Rong Gao, and David Z. Pan, "Triple-patterning Lithography (TPL) Layout Decomposition using End Cutting, " SPIE Intl. Symp. Advanced Lithography, San Jose, CA, Feb. 24-28, 2013.

[C143] Jhih-Rong Gao, Harshdeep Jawandha, Prasad Atkarc, Atul Walimbe, Bikram Baidya, and David Z. Pan, "Self-aligned Double Patterning Compliant Routing with In-design Physical Verification Flow, " SPIE Intl. Symp. Advanced Lithography, San Jose, CA, Feb. 24-28, 2013.

[C142] Jhih-Rong Gao, Bei Yu, Ru Huang, and David Z. Pan, "Self-aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement, " SPIE Intl. Symp. Advanced Lithography, San Jose, CA, Feb. 24-28, 2013.

[C141] Bei Yu, Jhih-Rong Gao, and David Z. Pan, "L-Shape based Layout Fracturing for E-Beam Lithography, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, January 22- 25, 2013. (Best Paper Award Nomination)

[C140] Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-seok Yang, Kun Yuan, Minsik Cho, and David Z. Pan, "Dealing with IC Manufacturability in Extreme Scaling, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 5-8, 2012. (Embedded Tutorial Paper)

[C139] Jiwoo Pak, Sung Kyu Lim, and David Z. Pan, "Electromigration-aware Routing for 3D ICs with Stress-aware EM Modeling, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-8, 2012.

[C138] Yen-Hung Lin, Bei Yu, David Z. Pan and Yih-Lang Li, "TRIAD: A Triple Patterning Lithography Aware Detailed Router, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-8, 2012.

[C137] Yilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, and David Z. Pan, "Reclaiming Over-the-IP-Block Routing Resources With Buffering-Aware Rectilinear Steiner Minimum Tree Construction, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-8, 2012.

[C136] Jiwoo Pak, Mohit Pathak, Sung Kyu Lim, and David Z. Pan, "Modeling and Prediction of Chip-level Electromigration for TSV-based 3D ICs", SRC Techcon Conference, Austin, TX, Sept. 10-11, 2012. (Best in Session Award)

[C135] Samuel I. Ward, Duo Ding, and David Z. Pan, "PADE: A High-Performance Mixed-Size Placer with Automatic Datapath Extraction and Evaluation through High-Dimensional Data Learning, " ACM/IEEE Design Automation Conference (DAC) , 2012.

[C134] Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Chip/Package Co-Analysis of Thermo-Mechanical Stress and Reliability in TSV-based 3D ICs, " ACM/IEEE Design Automation Conference (DAC) , 2012. (Nominated for Best Paper Award)

[C133] David Z. Pan, Jhih-Rong Gao and Bei Yu, "VLSI CAD for Emerging Nanolithography, " International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2012. (Invited Paper)

[C132] Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles Alpert, Earl Swartzlander, and David Z. Pan, "Keep it Straight: Teaching Placement how to Better Handle Designs with Datapaths, " ACM International Symposium on Physical Design (ISPD), Napa Valley, CA, March, 2012. (Nominated for Best Paper Award)

[C131] Jhih-Rong Gao an David Z. Pan, "Flexible Self-aligned Double Patterning Aware Detailed Routing with Prescribed Layout Planning, " ACM International Symposium on Physical Design (ISPD), Napa Valley, CA, March, 2012

[C130] Kevin Lucas, Chris Cork, Gerry Luk-Pat, Ben Painter, Bei Yu, and David Z. Pan, "Implications of triple patterning for 14 nm node design and patterning, " SPIE Advanced Lithography Symposium Design for Manufacturability through Design-Process Integration VI (Conference 8327), Feb. 2012. (Keynote Presentation and Invited Paper)

[C129] Vijay J. Reddi, David Z. Pan, Sani R. Nassif, and Keith A. Bowman, "Robust and Resilient Designs from the Bottom-Up: Technology, Circuit, CAD and System Issues, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Sydney, Australia, Jan. 30-Feb. 3, 2012. (Invited Special Session Paper)

[C128] David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, and Jae-seok Yang, "Design for Manufacturability and Reliability for TSV-based 3D ICs, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Sydney, Australia, Jan. 30-Feb. 3, 2012. (Invited Special Session Paper)

[C127] Duo Ding, Bei Yu, Joydeep Ghosh, and David Z. Pan, "EPIC: Efficient Prediction of IC Manufacturing Hotspots With A Unified Meta-Classification Formulation, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Sydney, Australia, Jan. 30-Feb. 3, 2012. (Best Paper Award)

[C126] Duo Ding, Bei Yu, and David Z. Pan, "GLOW: A Global Router for Low-Power Thermal-reliable Interconnect Synthesis using Photonic Wavelength Multiplexing, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Sydney, Australia, Jan. 30-Feb. 3, 2012

[C125] Duo Ding and David Z. Pan, "Low-power Integration of On-chip Nanophotonic Interconnect for High-performance Opto-electrical IC, " Proc. SPIE Optoelectronic Integrated Circuits XIV, Jan. 25-26, 2012 (Invited Paper)

[C124] Ryan A. Integlia, Lianghong Yin, Duo Ding, David Z. Pan, Douglas M. Gill, and Wei Jiang, "Parallel-coupled dual racetrack silicon micro-resonators for quadrature amplitude modulation" Proc. SPIE Silicon Photonics VII , Jan. 22-25, 2012

[C123] Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding and David Z. Pan, "Layout Decomposition for Triple Patterning Lithography, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011 (Finalist for William J. McCalla Best Paper Award)

[C122] Yen-Hung Lin, Yong-Chan Ban, David Z. Pan and Yih-Lang Li, "DOPPLER: DPL-aware and OPC-friendly Gridless Detailed Routing with Mask Density Balancing, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011

[C121] Moongon Jung, Xi Liu, Suresh Sitaraman, David Z. Pan and Sung Kyu Lim, "Full-Chip Through-Silicon-Via Interfacial Crack Analysis and Optimization for 3D IC, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011

[C120] Mohit Pathak, Jiwoo Pak, David Z. Pan and Sung Kyu Lim, "Electromigration Modeling and Full-chip Reliability Analysis for BEOL Interconnect in TSV-based 3D ICs, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011

[C119] Wooyoung Jang, Ou He, Jae-Seok Yang and David Z. Pan, "Chemical-Mechanical Polishing Aware Application-Specific 3D NoC Design, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011

[C118] Moongon Jung, Joydeep Mitra, David Z. Pan, and Sung Kyu Lim, "TSV Stress-aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC, " ACM/IEEE Design Automation Conference (DAC), San Diego, June 2011. (Nominated for Best Paper Award)

[C117] Yongchan Ban, Kevin Lucas, and David Z. Pan, "Flexible 2D Layout Decomposition Framework for Spacer-type Double Pattering Lithography, " ACM/IEEE Design Automation Conference (DAC), San Diego, June 2011.

[C116] Duo Ding, Jhih-Rong Gao, Kun Yuan and David Z. Pan "AENEID: A Generic Lithography-friendly Detailed Router based on Post RET Data Learning and Hotspot Detection, " ACM/IEEE Design Automation Conference (DAC), San Diego, June 2011.

[C115] Yongchan Ban and Jae-Seok Yang, "Layout Aware Line-Edge Roughness Modeling and Poly Optimization for Leakage Minimization, " ACM/IEEE Design Automation Conference (DAC), San Diego, June 2011.

[C114] Joydeep Mitra, Moongon Jung, Rui Huang, Suk-Kyu Ryu, Sung Kyu Lim, and David Z. Pan, "A Fast Simulation Framework for Full-Chip Thermo-Mechanical Stress and Reliability Analysis of Through-Silicon-Via based 3D ICs, " IEEE Electronic Components and Technology Conference (ECTC), May 2011.

[C113] Jiwoo Pak, Mohit Pathak, Sung Kyu Lim and David Z. Pan, "Modeling of Electromigration in Through-Silicon-Via Based 3D IC, " IEEE Electronic Components and Technology Conference (ECTC), May 2011.

[C112] Kun Yuan and David Z. Pan, "E-Beam Lithography Stencil Planning and Optimization with Overlapped Characters, " ACM International Symposium on Physical Design (ISPD), March 2011 (Best Paper Award)

[C111] Yongchan Ban, Soo-Han Choi, Kevin Lucas, Chul-Hong Park and David Z. Pan, "Layout Decomposition of Self-Aligned Double Patterning for 2D Random Logic Patterning, " SPIE Intl. Symp. Advanced Lithography, February 27 - March 3, 2011

[C110] Chul-Hong Park, David Z. Pan, and Kevin Lucas, "Exploration of VLSI CAD Researches for Early Design Rule Evaluation, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 2011 (Invited Paper)

[C109] Duo Ding, Andres J. Torres, Fedor G. Pikus and David Z. Pan, "High Performance Lithographic Hotspot Detection using Hierarchically Refined Machine Learning, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 2011

[C108] Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim and David Z. Pan, "Robust Clock Tree Synthesis with Timing Yield Optimization for 3DICs, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 2011

[C107] Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, and Giovanni De Micheli, "CELONCEL: Effective Design Technique for 3D Monolithic Integration targeting High Performance Integrated Circuits, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 2011

[C106] Ashutosh Chakraborty and David Z.Pan, "Controlling NBTI Degradation during Static Burn-in Testing, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 2011

[C105] Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan and Sung Kyu Lim, "Stress-Driven 3D-IC Placement with TSV Keep-Out Zone and Regularity Study, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2010, San Jose, CA, November 2010

[C104] Minsik Cho, David Z. Pan and Ruchir Puri, "Novel Binary Linear Programming for High Performance Clock Mesh Synthesis, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2010, San Jose, CA, November 2010

[C103] Kun Yuan and David Z. Pan, "WISDOM: Wire Spreading Enhanced Decomposition of Masks in Double Patterning Lithography", IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2010, San Jose, CA, November 2010.

[C102] Ashutosh Chakraborty and David Z. Pan, "PASAP: Power Aware Structured ASIC Placement, " IEEE International Symposium on Low Power Electronics Design (ISLPED), Austin, TX, August 2010. Slides

[C101] David Z. Pan, Jae-Seok Yang, Kun Yuan, and Minsik Cho, "CAD for Double Patterning Lithography", IEEE International Conference on IC Design and Technology (ICICDT), Grenoble, France, June 2010 (Invited Paper)

[C100] Wooyoung Jang, Duo Ding and David Z. Pan, "Voltage and Frequency Island Optimizations for Many-core/NoC Designs, " The First International Conference on Green Circuits and Systems (ICGCS) , Shanghai, China, June 2010 (Invited Paper)

[C99] Wooyoung Jang and David Z. Pan, "Application-Aware NoC Design for Efficient SDRAM Access, " ACM/IEEE Design Automation Conference (DAC), California, June 2010

[C98] Yongchan Ban and David Z. Pan, "Compact Modeling and Robust Layout Optimization for Contacts in Deep Subwavelength Lithography, " ACM/IEEE Design Automation Conference (DAC), California, June 2010.

[C97] Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, and David Z. Pan, "TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization, " ACM/IEEE Design Automation Conference (DAC), California, June 2010.

[C96] Anurag Kumar, Minsik Cho, and David Z. Pan, "DNA Microarray Placement for Improved Performance and Reliability, " International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2010.

[C95] Yongchan Ban, S. Sundareswaran, and David Z. Pan, "Total Sensitivity Based DFM Optimization of Standard Library Cells, " ACM International Symposium on Physical Design (ISPD), San Francisco, California, March 2010.

[C94] Ashutosh Chakraborty and David Z. Pan, "Skew Management of NBTI Impacted Gated Clock Trees, " ACM International Symposium on Physical Design (ISPD), San Francisco, California, March 2010. (Nominated for Best Paper Award) Slides

[C93] Yongchan Ban, Yuansheng Ma, Harry J. Levinson, Yunfei Deng, Jongwook Kye, and David Z. Pan, "Modeling and characterization of contact edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell, " SPIE Intl.Symp. Advanced Lithography, February 2010

[C92] Wooyoung Jang, David Z. Pan, "A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Taiwan, Jan. 2010.

[C91] Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, and David Z. Pan, "A New Graph Theoretic, MultiObjective Layout Decomposition Framework for Double Patterning Lithography, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Taiwan, Jan. 2010. (Best Paper Award)
(IBM Research Pat Goldberg Memorial Best Paper Award for 2010 in Computer Science, Electrical Engineering and Math)

[C90] David Z. Pan, Jae-seok Yang, Kun Yuan, Minsik Cho, and Yongchan Ban, "Layout Optimizations for Double Patterning Lithography, " IEEE 8th International Conference on ASIC (ASICON), Changsha, China, Oct. 2009. (Invited Paper)

[C89] Yongchan Ban, Savithri Sundareswaran, and David Z. Pan, "Comprehensive Standard Cell Characterization Considering Random Line-Edge Roughness Lithography Variation, " , SRC Techcon Conference, Austin, TX, September 2009.

[C88] Katrina Lu and David Z. Pan, "Reliability-aware Global Routing under Thermal Considerations, " Asia Symposium on Quality Electronic Design (ASQED), Malaysia, July 2009.

[C87] Duo Ding and David Z. Pan, "OIL: A Nanophotonic Optical Interconnect Library for a New Photonic Networks-on-Chip Architecture, " International Workshop on System Level Interconnect Prediction (SLIP), California, July 2009.

[C86] Kun Yuan, Katrina Lu, and David Z. Pan, "Double Patterning Lithography Friendly Detailed Routing with Redundant Via Consideration, " ACM/IEEE Design Automation Conference (DAC), California, July 2009.

[C85] Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, and David Z. Pan, "O-Router: An Optical Routing Framework for Low Power On-Chip Silicon Nano-Photonic Integration, " ACM/IEEE Design Automation Conference (DAC), California, July 2009.

[C84] Ashutosh Chakraborty, Anurag Kumar, and David Z. Pan, "RegPlace: A High Quality Opensource Placement Framework for Structured ASICs, " ACM/IEEE Design Automation Conference (DAC), California, July 2009. (Grand Prize $25,000 Winner of the eASIC Placement Worldwide Contest)

[C83] Wooyoung Jang and David Z. Pan, "An SDRAM-Aware Router for Networks-on-Chip, " ACM/IEEE Design Automation Conference (DAC), California, July 2009.

[C82] Duo Ding, Xiang Wu, Joydeep Ghosh, and David Z. Pan, "Machine Learning based Lithographic Hotspot Detection with Critical Feature Extraction and Classification, " IEEE International Conference on IC Design and Technology (ICICDT), Austin, TX, May 2009. (Best Student Paper Award)

[C81] Yong-Chan Ban, David Z. Pan, Savithri Sundareswaran and Rajendran Panda, "Electrical Impact of Line-Edge Roughness on Sub-45nm Node Standard Cell, " Intl.Symp. SPIE Advanced Lithography, February 2009.

[C80] Kun Yuan, Jae-Seok Yang and David Z. Pan, "Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization, " ACM International Symposium on Physical Design (ISPD), San Diego, March 2009.

[C79] Ashutosh Chakraborty and David Z. Pan, "On Stress Aware Active Area Sizing, Gate Sizing, and Repeater Insertion, " ACM International Symposium on Physical Design (ISPD), San Diego, March 2009.

[C78] Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram and David Z. Pan, "Analysis and Optimization of NBTI Induced Clock Skew in Gated Clock Trees, " IEEE/ACM Design, Automation & Test in Europe (DATE), Nice, France, April 2009. (Best Paper/IP Award)

[C77] Peng Yu, Xi Chen, David Z. Pan, and Andrew Ellington, "Synthetic Biology Design and Analysis: a Case Study of Frequency Entrained Biological Clock, " IEEE International Conference on Bioinformatics and Biomedicine (BIBM'08), November 2008.

[C76] David Z. Pan, Minsik Cho, Kun Yuan, and Yongchan Ban, "Lithography Friendly Routing: From Construct-by-Correction to Correct-by-Construction, " IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Beijing, October 2008. (Invited Paper)

[C75] Shanhu Shen, Peng Yu, and David Z. Pan, "Enhanced DCT2-based Inverse Mask Synthesis with Initial SRAF Insertion", SPIE/BACUS Photomask Symposium, October 2008.

[C74] Jae-Seok Yang and David Z. Pan, "Overlay Aware Interconnect and Timing Variation Modeling for Double Patterning Technology, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2008

[C73] Wooyoung Jang, Duo Ding and David Z. Pan, "A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2008.

[C72] Tao Luo, David A. Papa, Zhuo Li, C. N. Sze, Charles J. Alpert and David Z. Pan, "Pyramids: An Efficient Computational Geometry-based Approach for Timing-driven Placement, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2008. (Nominated for Best Paper Award)

[C71] Minsik Cho, Yongchan Ban and David Z. Pan, "Double Patterning Technology Friendly Detailed Routing, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2008.

[C70] Anand Rajaram and David Z. Pan, "Robust Chip-Level Clock Tree Synthesis for SOC Designs, " ACM/IEEE Design Automation Conference (DAC), California, June 2008.

[C69] Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan, "An Integrated Nonlinear Placement Framework with Congestion and Porosity Aware Buffer Planning, " ACM/IEEE Design Automation Conference (DAC), California, June 2008.

[C68] Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan, "ELIAD: Efficient Lithography Aware Detailed Router with Compact Printability Prediction, " ACM/IEEE Design Automation Conference (DAC), California, June 2008.

[C67] Tung-Chieh Chen, Minsik Cho, David Z. Pan and Yao-Wen Chang, "Metal-Density Driven Placement for CMP Variation and Routability, " ACM International Symposium on Physical Design (ISPD), Portland, April 2008.

[C66] Minsik Cho and D. Z. Pan, "A High-Performance Droplet Router for Digital Microfluidic Biochips, " ACM International Symposium on Physical Design (ISPD), Portland, April 2008.

[C65] S. X. Shi, A. Ramalingam, D. Wang, and D. Z. Pan, "Latch Modeling for Statistical Timing Analysis, " IEEE/ACM Design, Automation & Test in Europe (DATE), Munich, Germany, March 2008.

[C64] Ashutosh Chakraborty, S. X Shi, David Z. Pan, "Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices, " IEEE/ACM Design, Automation & Test in Europe (DATE), Munich, Germany, March 2008.

[C63] David Z. Pan and Minsik Cho, "Synergistic Physical Synthesis for Manufacturability/Variability in 45nm Designs and Beyond, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008. (Invited Paper)

[C62] Tao Luo, David Z. Pan, "DPlace 2.0: A Stable and Efficient Analytical Placement based on Diffusion, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008.

[C61] Tao Luo, David Newmark, David Z. Pan, "Total Power Optimization Combining Placement, Sizing and Multi-Vt Through Slack Distribution Management, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008.

[C60] Anand Rajaram and David Z. Pan, "MeshWorks: An Efficient Framework for Planning, Synthesis and Optimization of Clock Mesh Networks, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008. (Nominated for Best Paper Award)

[C59] Peng Yu and David Z. Pan, "TIP-OPC: A New Topological Invariant Paradigm for Pixel Based Optical Proximity Correction, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2007.

[C58] Peng Yu and David Z. Pan, "A Novel Intensity Based OPC Algorithm with Speedup in Lithography Simulation, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2007.

[C57] Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan, "BoxRouter 2.0: Architecture and Implementation of a Hybrid and Robust Global Router, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2007.

[C56] Peng Yu and David Z. Pan, "TIP-OPC: A New Topological Invariant Paradigm for Pixel Based Optical Proximity Correction", SRC Techcon Conference, September, 2007.

[C55] Tao Luo, David Newmark, David Z. Pan, "Effective Power Optimization combining Placement, Sizing and Multi-Vt techniques", SRC Techcon Conference, September, 2007 (Best Paper in Session)

[C54] Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky and David Z. Pan, "Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis, " ACM/IEEE Design Automation Conference (DAC), June, 2007.

[C53] Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "TROY: Track Router with Yield-driven Wire Planning, " ACM/IEEE Design Automation Conference (DAC), June 2007.

[C52] Joon-Sung Yang, Anand Rajaram, Ningyu Shi, Jian Chen and David Z. Pan, "Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis, " International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2007.

[C51] A. Ramalingam, G.V. Devarayanadurg, and D. Z. Pan, "Accurate Power Grid Analysis with behavioral Transistor Network Modeling, " International Symposium on Physical Design (ISPD), Austin, March 2007.

[C50] P. Yu and D. Z. Pan, "Fast Predictive Post-OPC Contact/Via Printability Metric and Validation, " Proc. of SPIE Optical Microlithography XX,  Vol. 6520, 2007.

[C49] Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky and David Z. Pan, "Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis, " ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Austin, Texas, Feb  2007.

[C48] H. Ren, D. Z. Pan, C. Alpert, G.-J. Nam, and P. Villarrubia, "Hippocrates: First-Do-No-Harm Detailed Placement'', IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2007.

[C47] M. Cho, H. Xiang, R. Puri, and D. Z. Pan, "Wire Density Driven Global Routing for CMP Variation and Timing, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2006.

[C46] S. X Shi, P. Yu, and D. Z. Pan, "A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2006.

[C45] A. Ramalingam, A. K. Singh, S. R. Nassif, G.-J. Nam, M. Orshansky, and D. Z. Pan, "An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2006.

[C44] A. Dutta and D. Z. Pan, "Partial Functional Manipulation Based Wirelength Minimization, " IEEE International Conference on Computer Design (ICCD), Oct. 2006.

[C43] P. Yu, S. X. Shi and D. Z. Pan, "Process Variation Aware OPC with Variational Lithography Modeling, " ACM/IEEE Design Automation Conference (DAC), San Francisco, California, July, 2006.

[C42] M. Cho and D. Z. Pan, "BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP, " ACM/IEEE Design Automation Conference (DAC), San Francisco, California, July, 2006. (Nominated for Best Paper Award, 12 out of 865 submissions)

[C41] T. Luo, D. Newmark and D. Z. Pan, "A New LP Based Incremental Timing Driven Placement for High Performance Designs, " ACM/IEEE Design Automation Conference (DAC), San Francisco, California, July, 2006.

[C40] M. Cho and D. Z. Pan, "PEAKASO: Peak-Temperature Aware Scan-Vector Optimization, " VLSI Test Symposium, Berkeley, CA (VTS), May 2006.

[C39] A. Rajaram and D. Z. Pan, Variation Tolerant Buffered Clock Network Synthesis with Cross Links, " ACM International Symposium on Physical Design (ISPD), San Francisco, CA, April 2006. (covered by EE Times on April 17, 2006 in the report "Paths to better timing analysis, "by Richard Goering)

[C38] A. Havlir and D. Z. Pan, "Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines, " IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2006.

[C37] A. Ramalingam, F. Liu, S. R. Nassif, and D. Z. Pan, "Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity, " IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2006.

[C36] A. Rajaram and D. Z. Pan, "Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction, " IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2006.

[C35] P. Yu, D. Z. Pan and C. A. Mack, Fast Lithography Simulation under Focus Variations for OPC and Layout Optimizations, " SPIE Design and Process Integration for Microelectronic Manufacturing IV, Feb. 2006.

[C34] M. Cho, H. Shin and D. Z. Pan, "Fast Substrate Noise-Aware Floorplanning with Preference Directed Graph for Mixed-Signal SOCs, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2006, (Nominated for Best Paper Award, 8 out of 424 submissions).

[C33] S. X. Shi and D. Z. Pan, "Wire Sizing and Shaping with Scattering Effect for Nanoscale Interconnection, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2006.

[C32] A. Ramalingam, S. V. Kodakara, A. Devgan and D. Z. Pan, "Robust Analytical Gate Delay Modeling for Low Voltage Circuits, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2006.

[C31] T. Luo, H. Ren, C. Alpert and D. Z. Pan, "Computational Geometry Based Placement Migration, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2005.

[C30] M. Cho, S. Ahmed and D. Z. Pan, "TACO: Temperature Aware Clock Optimization, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2005. (covered by EE Times on June 19, 2006 in the report "Chip designers feel the heat, "by Richard Goering)

[C29] D. Z. Pan, "Lithography Aware Physical Design, " IEEE 6th International Conf. on ASIC (ASICON), Shanghai, Oct. 24-27, 2005. (Invited Paper at the Special Session on DFM)

[C28] J. Mitra, P. Yu and D. Z. Pan, "RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations, " ACM/IEEE Design Automation Conference (DAC), Anaheim, California, June, 2005.

[C27] H. Ren, D. Z. Pan, C. Alpert and P. Villarrubia, "Diffusion Based Placement Migration, " ACM/IEEE Design Automation Conference (DAC), Anaheim, California, June, 2005.

[C26] D. Z. Pan and M. D. F. Wong, "Manufacturability Aware Physical Layout Optimizations, " IEEE International Conference on IC Design and Technology (ICICDT), Austin, TX, May 2005. (Invited Paper)

[C25] J. Mitra and P. Yu and D. Z. Pan, "RADAR: RET-Aware Detailed Routing", Electronic Design Process (EDP) Workshop, Monterey, California, April, 2005.

[C24] H. Ren, D. Z. Pan, C. Alpert and P. Villarrubia, "Diffusion Based Placement Migration", Electronic Design Process (EDP) Workshop,  Monterey, California, April, 2005.

[C23] A. Rajaram, D. Z. Pan and J. Hu, "Improved Algorithms for Link Based Non-tree Clock Network for Skew Variability Reduction, " ACM International Symposium on Physical Design (ISPD), San Francisco, CA, April 2005.

[C22] A. Ramalingam, B. Zhang, A. Devgan, and D. Z. Pan, "Sleep Transistor Sizing Using Timing Criticality and Temporal Currents, " IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2005.

[C21] G. Xu, L. Huang, D. Z. Pan and M. D.-F. Wong, "Redundant-Via Enhanced Maze Routing for Yield Improvement, " IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC),  Jan. 2005.

[C20] G. Xu, R. Tian, D. Z. Pan and M. D.-F. Wong, "CMP Aware Shuttle Mask Floorplanning, " IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2005.

[C19] H. Ren, D. Z. Pan and P. Villarrubia, "True Crosstalk Aware Incremental Placement with Noise Map, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2004.

[C18] G. Xu, R. Tian, D. Z. Pan and M. D.F. Wong, "A Multi-objective Floorplanner for Shuttle Mask Optimization, " SPIE International Symp. on Photomask Technology, Sept. 2004.

[C17] H. Ren, D. Z. Pan and D. S. Kung, "Sensitivity Guided Netweighting for Placement Driven Synthesis, " ACM International Symposium on Physical Design (ISPD), Phoenix, Arizona, April 2004.

[C16] R. Puri, L. Stok, J. Cohn, D. Kung, D. Z. Pan, D. Sylvester, A. Srivastava, and S. H. Kulkarni, "Pushing ASIC Performance in a Power Envelope, " ACM/IEEE Design Automation Conference (DAC), Anaheim, California, June, 2003.

[C15] D. Z. Pan, A. Correale, D. Lamb, D. Wallach, D. Kung, and R. Puri, "Generic Voltage Island: CAD Flow and Design Experience", Austin Conference on Energy Efficient Design (ACEED), Austin, Texas, Feb, 2003.

[C14] R. Puri, D. Z. Pan and D. Kung, "A Flexible Design Approach for the Use of Dual Supply Voltages and Level Conversion for Low-Power ASIC Design", Austin Conference on Energy Efficient Design (ACEED), Austin, Texas, Feb, 2003.

[C13] C.-C. Chang, J. Cong, D. Z. Pan and X. Yuan, "Physical Hierarchy Generation with Routing Congestion and Control, " ACM International Symposium on Physical Design (ISPD), pp36-41, San Diego, California, April 2002.

[C12] J. Cong, D. Z. Pan and P.V. Srinivas, "Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization, " IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), Jan. 30 - Feb. 2, 2001, Pacifico Yokohama, Japan.

[C11] J. Cong, D. Z. Pan and P.V. Srinivas, "Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization, " ACM TAU Workshop, Dec. 4-5, 2000, Austin.

[C10] C.-C. Chang, J. Cong, D. Z. Pan and X. Yuan, " Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization, " SRC Techcon Conference, September 21-3, 2000, Phoenix.

[C9] J. Cong, D. Z. Pan and P.V. Srinivas, " Improved Crosstalk Modeling with Applications to Noise Constrained Interconnect Optimization, " SRC Techcon Conference, September 21-3, 2000, Phoenix.

[C8] J. Cong, T. Kong and D. Z. Pan, "Buffer Block Planning for Interconnect-Driven Floorplanning, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , November, 1999.

[C7] J. Cong and D. Z. Pan, "Interconnect Estimation and Planning for Deep Submicron Designs, " ACM/IEEE 36th Design Automation Conference (DAC) , June 20-5, 1999, New Orleans.

[C6] J. Cong and D. Z. Pan, "Interconnect Delay and Area Estimation for Multiple-Pin Nets, " ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 8-9, 1999, Monterey. 

[C5] J. Cong and D. Z. Pan, "Interconnect Delay Estimation Models for Synthesis and Design Planning, " IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), January 18-21, 1999, Hong Kong.

[C4] J. Cong and D. Z. Pan, "Interconnect Delay Estimation Models for Logic and High Level Synthesis, " SRC Techcon Conference, September 9-11, 1998, Las Vegas. (Best Paper in Session Award)

[C3] J. Cong and D. Z. Pan, " Interconnect Performance Estimation Models for Synthesis and Design Planning, " ACM/IEEE International Workshop on Logic Synthesis, June, 1998.

[C2] J. Cong, L. He, C.-K. Koh and Z. Pan,  "Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 1997.

[C1] J. Cong, L. He, K.-Y. Khoo, C.-K. Koh and Z. Pan, "Interconnect Design for Deep Submicron ICs, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 1997. (Embedded Tutorial)


JOURNAL ARTICLES PAPERS (Go to Top)

[J82] Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert and David Z. Pan, "MrDP: Multiple-row Detailed Placement of Heterogeneous-sized Cells for Advanced Nodes, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J81] Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, and David. Z. Pan, "Provably Secure Camouflaging Strategy for IC Protection, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J80] Xiaoqing Xu, Yibo Lin, Meng Li, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, and David Z. Pan, "Sub-Resolution Assist Feature Generation with Supervised Data Learning, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J79] Hengliang Zhu, Feng Hu, Hao Zhou, Dian Zhou, Xuan Zeng, and David Z. Pan, "Interlayer Cooling Network Design for High-Performance 3D-ICs Using Channel Patterning and Pruning, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J78] Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Changhao Yan, Dian Zhou, and Xuan Zeng, "An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation, " ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017. (accepted)

[J77] Wuxi Li, Shounak Dhar, and David Z. Pan, "UTPlaceF: A Routability-Driven FPGA Placer with Physical and Congestion Aware Packing, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J76] Yibo Lin, Xiaoqing Xu, Bei Yu, Ross Baldick and David Z. Pan, "Triple/quadruple patterning layout decomposition via novel linear programming and iterative rounding, " Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), 2017. (accepted)

[J75] Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, and David Z. Pan, "Stitch Aware Detailed Placement for Multiple E-Beam Lithography, " Integration, the VLSI Journal, 2017. (accepted)

[J74] Taehee Lee, David Z. Pan, and Joon-Sung Yang, "Clock Network Optimization with Multi-bit Flip-flop Generation Considering Multi-corner Multi-mode Timing Constraint, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J73] Derong Liu, Bei Yu, Salim Chowdhury, and David Z. Pan, "Incremental Layer Assignment for Timing Optimization, " ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017. (accepted)

[J72] Derong Liu, Bei Yu, Salim Chowdhury, and David Z. Pan, "TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J71] Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, and David Z. Pan, "Redundant Local-Loop Insertion for Unidirectional Routing, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J70] Yibo Lin, Bei Yu, Biying Xu, and David Z. Pan, "Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J69] Yibo Lin, Bei Yu, and David Z. Pan, "High Performance Dummy Fill Insertion with Coupling and Uniformity Constraints, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J68] Vinicius Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, Jose Luıs Guntzel, and Luiz C. V. dos Santos, "Incremental Layer Assignment Driven by an External Signoff Timing Engine, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. (accepted)

[J67] Xiaoqing Xu and David Z. Pan, "Toward Unidirectional Routing Closure in Advanced Technology Nodes, " IPSJ Transactions on System LSI Design Methodology, Vol.10, pp. 1–12, Apr. 2017. (Invited Paper)

[J66] Tetsuaki Matsunawa, Bei Yu, and David Z Pan, "Laplacian Eigenmaps and Bayesian Clustering Based Layout Pattern Sampling and Its Applications to Hotspot Detection and OPC, " Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), 2016.

[J65] Tetsuaki Matsunawa, Bei Yu, and David Z Pan, "Optical Proximity Correction with Hierarchical Bayes Model, " The Journal of Microlithography, Microfabrication, and Microsystems (JM3), 2016.

[J64] Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, and David. Z. Pan, "OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations under Multiple Operating Conditions, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.

[J63] Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, and David Z. Pan, "Design for Manufacturability and Reliability in Extreme-Scaling VLSI, " Science China Information Sciences (SCIS), vol.59, 061406:2, June, 2016. (Invited Paper)

[J62] Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, and Xuan Zeng, "Layout Decomposition Co-optimization for Hybrid E-Beam and Multiple Patterning Lithography, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2015.

[J61] Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, and David Z. Pan, "PARR: Pin Access Planning and Regular Routing for Self-Aligned Double Patterning, " ACM Transactions on Design Automation of Electronic Systems (TODAES), 2015.

[J60] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu and David Z. Pan, "A Systematic Framework for Evaluating Standard Cell Middle-Of-Line (MOL) Robustness for Multiple Patterning Lithography, " Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), 2015.

[J59] Subhendu Roy, Mihir Choudhury, Ruchir Puri and David Z. Pan, "Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2015.

[J58] Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, and Xuan Zeng, "Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography, " ACM Transactions on Design Automation of Electronic Systems, 2015.

[J57] Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, and David Z. Pan, "Directed self-assembly cut mask assignment for unidirectional design, " J. Micro/Nanolith. MEMS MOEMS. (JM3), 14(3), 031211, Aug 07, 2015.

[J56] Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles Alpert, and David Z. Pan, "Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 5, pp. 726-739, 2015.

[J55] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, and David Z. Pan, "Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 5, pp. 699-712, 2015.

[J54] Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, and David Z. Pan, "Clock Tree Resynthesis for Multi-corner Multi-mode Timing Closure, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 4, pp. 589-602, 2015.

[J53] Bei Yu, Kun Yuan, Duo Ding, and David Z. Pan, "Layout Decomposition for Triple Patterning Lithography, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 3, pp. 433-446, 2015.

[J52] Yongchan Ban and David Z. Pan, "Self-Aligned Double Patterning Layout Decomposition for 2D Random Metals for Sub-10nm Node Design, " The Journal of Microlithography, Microfabrication, and Microsystems (JM3), vol. 14, no. 1, pp. 011004, Jan-Mar 2015

[J51] Bei Yu, Jhih-Rong Gao, Duo Ding, Xuan Zeng, and David Z. Pan, "Accurate Lithography Hotspot Detection based on Principal Component Analysis-Support Vector Machine Classifier with Hierarchical Data Clustering, " The Journal of Microlithography, Microfabrication, and Microsystems (JM3), vol. 14, no. 1, pp. 011003, Jan-Mar 2015

[J50] Bei Yu, Subhendu Roy, Jhih-Rong Gao, and David Z. Pan, "Triple Patterning Lithography Layout Decomposition Using End-cutting, " The Journal of Microlithography, Microfabrication, and Microsystems (JM3), vol. 14, no. 1, pp. 011002, Jan-Mar 2015

[J49] Jiwoo Pak, Sung Kyu Lim, and David Z. Pan, "Electromigration Study for Multi-scale Power/Ground Vias in TSV-based 3D ICs, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 12, Dec. 2014.

[J48] Subhendu Roy, Mihir Choudhury, Ruchir Puri, and David Z. Pan, "Toward Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 10, pp. 1517-1530, Oct. 2014.

[J47] Moongon Jung, Joydeep Mitra, David Z. Pan, and Sung Kyu Lim, "Full-Chip Mechanical Reliability Analysis and Optimization for 3D ICs, " Communications of the ACM, Jan. 2014. (Research Highlights)

[J46] Runsheng Wang, Xiaobo Jiang, Tao Yu, Jiewen Fan, Jiang Chen, David Z. Pan, and Ru Huang, "Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II -- Experimental Results and Impacts on Device Variability, " IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3676-3682, Nov. 2013.

[J45] David Z. Pan, Bei Yu, and Jhih-Rong Gao, "Design for Manufacturing with Emerging Nanolithography, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , 2013. (Keynote Paper)

[J44] Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Chip/Package Mechanical Stress Impact on 3D IC Reliability and Mobility Variations, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , 2013.

[J43] Wooyoung Jang and David Z. Pan, "Chemical-Mechanical Polishing Aware Application-Specific 3D NoC Design, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , 2013.

[J42] Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, and Sung Kyu Lim, "Impact of Mechanical Stress on the Full Chip Timing for TSV-based 3D ICs, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2013.

[J41] Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles Alpert, Earl E. Swartzlander Jr., and David Z. Pan, "Structure-Aware Placement Techniques for Designs with Datapath, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.

[J40] Wooyoung Jang and David Z. Pan, "A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip, " ACM Transactions on Design Automation of Electronic Systems (TODAES) . 2012

[J39] Moongon Jung, Joydeep Mitra, David Z. Pan, and Sung Kyu Lim, "TSV Stress-aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012. i

[J38] Ashutosh Chakraborty and David Z. Pan, "Skew Management of NBTI Impacted Gated Clock Trees, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.

[J37] Kun Yuan, Bei Yu and David Z. Pan, "E-Beam Lithography Stencil Planning and Optimization with Overlapped Characters, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 2, pp. 167-179, Feb. 2012.

[J36] Duo Ding, J. Andres Torres, and David Z. Pan, "High Performance Lithography Hotspot Detection with Successively Refined Pattern Identifications and Machine Learning, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 11, pp. 1621-1634, Nov. 2011.

[J35] Wooyoung Jang and David Z. Pan, "Application-Aware NoC Design for Efficient SDRAM Access, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2011

[J34] Wooyoung Jang and David Z. Pan, "A Voltage-Frequency Island aware Energy Optimization framework for networks-on-chip, " IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) , vol. 1, no. 3, pp. 420-432, September 2011.

[J33] Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, and David Z. Pan, "UNISM: Unified Scheduling and Mapping for General Networks on Chip, " IEEE Transactions on VLSI Systems (TVLSI), July 2011.

[J32] Ryan A. Integlia, Lianghong Yin, Duo Ding, David Z. Pan, Douglas M. Gill, and Wei Jiang, "Parallel-coupled dual racetrack silicon micro-resonators for quadrature amplitude modulation, " Optics Express, Vol. 19, Issue 16, pp. 14892-14902, 2011.

[J31] Yongchan Ban and David Z. Pan "Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization, " IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2011.

[J30] Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky and David Z. Pan "An accurate sparse-matrix based framework for statistical static timing analysis, " Integration, the VLSI Journal, 2011

[J29] Anand Rajaram and David Z. Pan, "Robust Chip-Level Clock Tree Synthesis, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2011

[J28] Anand Rajaram and David Z. Pan, "MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 29, Issue 12, pp. 1845-1958, Dec 2010.

[J27] Yongchan Ban, Yuansheng Ma, Harry J. Levinson, and David Z. Pan, "Modeling and Characterization of Contact-Edge Roughness for Minimizing Design and Manufacturing Variations, " The Journal of Microlithography, Microfabrication, and Microsystems (JM3), Nov. 2010.

[J26] Yongchan Ban, Savithri Sundareswaran and David Z. Pan, "Electrical Impact of Line-Edge Roughness on Sub-45nm Node Standard Cells, " The Journal of Microlithography, Microfabrication, and Microsystems (JM3), Nov. 2010.

[J25] Wooyoung Jang and David Z. Pan, "An SDRAM-Aware Router for Networks-on-Chip, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 29, Issue 10, pp. 1572 - 1585, Oct 2010.

[J24] Ashutosh Chakraborty, Sean X. Shi and David Z. Pan, "Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 29, Issue 10, pp. 1533 - 1545, Oct 2010.

[J23] Xinyuan Dou, Xiaolong Wang, Xiaohui Lin, Duo Ding, David Z. Pan and Ray T. Chen, "Highly Flexible Polymeric Optical Waveguide for Out-of-plane Optical Interconnects, " Optics Express, Vol.18, 16227-16233, July 2010.

[J22] Kun Yuan, Jae-Seok Yang and David Z. Pan, "Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),, Vol 29, Issue 2, pp. 185-196, Feb 2010

[J21] David Z. Pan, Minsik Cho, and Kun Yuan, "Manufacturability Aware Routing in Nanometer VLSI ", Foundations and Trends in Electronic Design Automation, Vol 4, No. 1, pp 1-97, Jan. 2010

[J20] Xinyuan Dou, Xiaolong Wang, Haiyu Huang, Xiaohui Lin, Duo Ding, David Z. Pan and Ray T. Chen, "Polymeric Waveguides with Embedded Micro-mirrors Formed by Metallic Hard Mold, " Optics Express, Vol.18, 16227-16233, Dec 2009

[J19] Minsik Cho, Kun Yuan, Yongchan Ban, and David Z. Pan, "ELIAD: Efficient Lithography Aware Detailed Routing Algorithm with Compact and Macro Post-OPC Printability Prediction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) Vol 28, Issue 7, pp. 1006-1016, July 2009

[J18] Peng Yu and David Z. Pan, "ELIAS: An Accurate and Extensible Lithography Aerial Image Simulator with Improved Numerical Algorithms, " IEEE Transactions on Semiconductor Manufacturing, Vol 22, No. 2, pp. 276-289, May 2009

[J17] Minsik Cho, Katrina Lu, Kun Yuan, and David Z. Pan, "BoxRouter 2.0: A Hybrid and Robust Global Router with Layer Assignment for Routability, " ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol 14, Issue 2, pp. 1-21, March 2009

[J16] Peng Yu, Weifeng Qiu and David Z. Pan, "Fast Lithography Image Simulation By Exploiting Symmetries in Lithography Systems, " IEEE Transactions on Semiconductor Manufacturing , Vol 21, Issue 4, pp. 638-645, Nov 2008

[J15] Tung-Chieh Chen, Minsik Cho, David Z. Pan and Yao-Wen Chang, "Metal-Density Driven Placement for CMP Variation and Routability, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , Vol 27, Issue 12, pp. 2145-2155, Dec 2008

[J14] Minsik Cho and David Z. Pan, "A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , Vol 27, Issue 10, pp. 1714-1724, Oct 2008

[J13] David Z. Pan, Peng Yu, Minsik Cho, Anand Ramalingam, Kiwoon Kim, Anand Rajaram and Sean X. Shi, "Design for Manufacturing Meets Advanced Process Control: A Survey, " Journal of Process Control, Vol 18, Issue 10, pp. 975-984, Dec 2008

[J12] Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "TROY: Track Routing and Optimization for Yield, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , Vol 27, Issue 5, pp. 872-882, May 2008

[J11] M. Cho and D. Z. Pan, "Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs, " IEEE Transactions on VLSI Systems, Vol 16, Issue 12, pp. 1713-1717, Dec 2008

[J10] H. Ren, D. Z. Pan, C. J. Alpert, P. Villarrubia, and G.-J. Nam, "Diffusion-Based Placement Migration with Application on Legalization, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 26, Issue 12, pp. 2158-2172, December 2007

[J9] M. Cho and D. Z. Pan, "BoxRouter: A New Global Router Based on Box Expansion, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 26, Issue 12, pp. 2130-2143, December 2007

[J8] P. Yu, S. X. Shi, and D. Z. Pan, "True Process Variation Aware Optical Proximity Correction with Variational Lithography Modeling and Model Calibration, " The Journal of Microlithography, Microfabrication, and Microsystems (JM3), Special Edition of Resolution Enhancement Techniques and Design for Manufacturability, September 2007

[J7] A. Ramalingam, A. Devgan, and D. Z. Pan, "Wakeup Scheduling in MTCMOS Circuits using Successive Relaxation to Minimize Ground Bounce, " ASP Journal of Low Power Electronics (JOLP), Vol 3, No. 1, April 2007

[J6] H. Ren, D. Z. Pan and D. S. Kung, "Sensitivity Guided Netweighting for Placement Driven Synthesis, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May, 2005.

[J5] C.-C. Chang, J. Cong, D. Z. Pan and X. Yuan, "Multilevel Global Placement with Congestion Control, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 4, pp.395-409, April 2003.

[J4] J. Cong and D. Z. Pan, "Wire Width Planning for Interconnect Performance Optimization, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 3, pp.319-329, March 2002.

[J3] J. Cong, T. Kong and D. Z. Pan, "Buffer Block Planning for Interconnect Planning and Prediction, " IEEE Transactions on VLSI Systems , vol. 9, no. 6, pp.929-937, December 2001.

[J2] J. Cong, L. He, C.-K. Koh and D. Z. Pan, "Interconnect Sizing and Spacing with Consideration of Coupling Capacitance, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp.1164-1169, September 2001.

[J1] J. Cong and D. Z. Pan, "Interconnect Performance Estimation Models for Design Planning, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 739--752, vol. 20, no. 6, June 2001


PATENTS (Go to Top)

[P8] Zhigang Pan and Peng Yu, "Method and System for Performing Optical Proximity Correction with Process Variations Considerations". US Patent, No. 7,711,504, Granted May 4, 2010

[P7] Minsik Cho and Zhigang Pan, "Method and Apparatus for Performing Global Routing on an Integrated Circuit Design". US Patent, No. 7,661,085, Granted on Feb. 9, 2010

[P6] Anthony Correale, Jr., David S. Kung, Douglas T. Lamb, Zhigang Pan, Ruchir Puri, David Wallach, "Multiple Voltage Integrated Circuit and Design Method Therefor". US Patent, No. 7,480,883, Granted on Jan. 20, 2009.

[P5] Anthony Correale, Jr., Rajeev Joshi, David S. Kung, Zhigang Pan, Ruchir Puri, "Single Supply Level Converter". US Patent, No. 7,119,578. Granted on Oct. 10, 2006.

[P4] Anthony Correale, Jr., David S. Kung, Douglas T. Lamb, Zhigang Pan, Ruchir Puri, David Wallach, "Multiple Voltage Integrated Circuit and Design Method Therefor", US Patent, No. 7,111,266, Granted on Sept. 19, 2006.

[P3] Anthony Correale, Jr., David S. Kung, Zhigang Pan, Ruchir Puri, "Method and Program Product of Level Converter Optimization", U.S. Patent, No. 7,089,510, Granted on August 8, 2006.

[P2] Jason Cong, Zhigang Pan, and P.V. Srinivas, "Method and Apparatus for Calculation of Crosstalk Noise in Integrated Circuits", U.S. Patent, No. 7,013,253. Granted March 2006.

[P1] Jason Cong and Zhigang Pan, "Wire Width Planning and Performance Optimization for VLSI Interconnects, U.S. Patent No. 6,408,427, Granted June 2002


 

 

 

 

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