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Jump to - Books/Books Chapters Conference Papers Journal Articles Patents
BOOKS / BOOK CHAPTERS (Go to Top)
[B4] D. Z. Pan and M. Stan, "Physical Design and Interaction with Technology" in CAD Algorithms, Methods and Tools For Low-Power Circuits and Systems (edited by Enrico Macii), Jan. 2006 (IEEE Technology Survey)[B3] D. Z. Pan, B. Halpin, and H. Ren, "Timing-Driven Placement" in Handbook of Algorithms for VLSI Physical Automation (edited by Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar), CRC Press, 2007 (Invited) (Amazon) (ISBN: 0849372429)
[B2] T. Luo and D. Z. Pan, "DPlace: Anchor Cell based Quadratic Placement with Linear Objective" in Modern Circuit Placement: Best Practices and Results (edited by Gi-Joon Nam and Jason Cong), Springer, 2007 (Invited) (Amazon) (ISBN: 038736837X)
[B1] M. Cho, J. Mitra, and D. Z. Pan, "Manufacturability Aware Routing" in Handbook of Algorithms for VLSI Physical Automation (edited by Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar), CRC Press, 2007 (Invited) (Amazon) (ISBN: 0849372429)
CONFERENCE PAPERS (Go to Top)
[C74] Jae-Seok Yang and David Z. Pan, "Overlay Aware Interconnect and Timing Variation Modeling for Double Patterning Technology", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD) 2008, (To appear)[C73] Wooyoung Jang, Duo Ding and David Z. Pan, "A Voltage-frequency Island Aware Energy Optimization Framework For Networks-on-Chip", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD) 2008, (To appear)
[C72] Tao Luo, David A. Papa, Zhuo Li, C. N. Sze, Charles J. Alpert and David Z. Pan, "Pyramids: An Efficient Computational Geometry-based Approach for Timing-driven Placement", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD) 2008, (To appear)
[C71] Minsik Cho, Yongchan Ban and David Z. Pan, "Double Patterning Technology Friendly Detailed Routing", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD) 2008, (To appear)
[C70] Anand Rajaram and David Z. Pan, "Robust Chip-Level Clock Tree Synthesis for SOC Designs", Design Automation Conference (DAC), California, June 2008
[C69] Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan, "An Integrated Nonlinear Placement Framework with Congestion and Porosity Aware Buffer Planning", Design Automation Conference (DAC), California, June 2008
[C68] Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan, "ELIAD: Efficient Lithography Aware Detailed Router with Compact Printability Prediction", Design Automation Conference (DAC), California, June 2008
[C67] Tung-Chieh Chen, Minsik Cho, David Z. Pan and Yao-Wen Chang, "Metal-Density Driven Placement for CMP Variation and Routability", International Symposium on Physical Design (ISPD), Portland, April 2008
[C66] Minsik Cho and D. Z. Pan, "A High-Performance Droplet Router for Digital Microfluidic Biochips", International Symposium on Physical Design (ISPD), Portland, April 2008
[C65] S. X. Shi, A. Ramalingam, D. Wang, and D. Z. Pan, "Latch Modeling for Statistical Timing Analysis", Design, Automation & Test in Europe (DATE), Munich, Germany, March 2008
[C64] Ashutosh Chakraborty, S. X Shi, David Z. Pan, "Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices", Design, Automation & Test in Europe (DATE), Munich, Germany, March 2008
[C63] David Z. Pan and Minsik Cho, "Synergistic Physical Synthesis for Manufacturability/Variability in 45nm Designs and Beyond", Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008 (Invited Paper)
[C62] Tao Luo, David Z. Pan, "DPlace 2.0: A Stable and Efficient Analytical Placement based on Diffusion", Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008
[C61] Tao Luo, David Newmark, David Z. Pan, "Total Power Optimization Combining Placement, Sizing and Multi-Vt Through Slack Distribution Management", Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008
[C60] Anand Rajaram and David Z. Pan, "MeshWorks: An Efficient Framework for Planning, Synthesis and Optimization of Clock Mesh Networks", Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008 (Nominated for Best Paper Award)
[C59] Peng Yu and David Z. Pan, "TIP-OPC: A New Topological Invariant Paradigm for Pixel Based Optical Proximity Correction", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), November 2007
[C58] Peng Yu and David Z. Pan, "A Novel Intensity Based OPC Algorithm with Speedup in Lithography Simulation", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), November 2007
[C57] Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan, "BoxRouter 2.0: Architecture and Implementation of a Hybrid and Robust Global Router", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), November 2007
[C56] Peng Yu and David Z. Pan, "TIP-OPC: A New Topological Invariant Paradigm for Pixel Based Optical Proximity Correction", Proc. SRC Techcon Conference, September, 2007
[C55] Tao Luo, David Newmark, David Z. Pan, "Effective Power Optimization combining Placement, Sizing and Multi-Vt techniques", Proc. SRC Techcon Conference, September, 2007 (Best Paper in Session)
[C54] Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky and David Z. Pan, "Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis", ACM/IEEE Design Automation Conference (DAC), June 2007
[C53] Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "TROY: Track Router with Yield-driven Wire Planning", ACM/IEEE Design Automation Conference (DAC), June 2007
[C52] Joon-Sung Yang, Anand Rajaram, Ningyu Shi, Jian Chen and David Z. Pan, "Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis", International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2007
[C51] A. Ramalingam, G.V. Devarayanadurg, and D. Z. Pan, "Accurate Power Grid Analysis with behavioral Transistor Network Modeling", International Symposium on Physical Design (ISPD), Austin, March 2007
[C50] P. Yu and D. Z. Pan, "Fast Predictive Post-OPC Contact/Via Printability Metric and Validation", Proc. of SPIE Optical Microlithography XX, Vol. 6520, 2007
[C49] Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky and David Z. Pan, "Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis", ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Austin, Texas, Feb 2007
[C48] H. Ren, D. Z. Pan, C. Alpert, G.-J. Nam, and P. Villarrubia, "Hippocrates: First-Do-No-Harm Detailed Placement'', Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2007
[C47] M. Cho, H. Xiang, R. Puri, and D. Z. Pan, "Wire Density Driven Global Routing for CMP Variation and Timing", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), November, 2006
[C46] S. X Shi, P. Yu, and D. Z. Pan, "A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), November, 2006
[C45] A. Ramalingam, A. K. Singh, S. R. Nassif, G.-J. Nam, M. Orshansky, and D. Z. Pan, "An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), November, 2006
[C44] A. Dutta and D. Z. Pan, "Partial Functional Manipulation Based Wirelength Minimization", Prof. IEEE Int'l Conference on Computer Design (ICCD), Oct. 2006.
[C43] P. Yu, S. X. Shi and D. Z. Pan, "Process Variation Aware OPC with Variational Lithography Modeling", Proc.43rd ACM/IEEE Design Automation Conference (DAC), San Francisco, California, July, 2006.
[C42] M. Cho and D. Z. Pan, "BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP", Proc.43rd ACM/IEEE Design Automation Conference (DAC), San Francisco, California, July, 2006 (Nominated for Best Paper Award, 12 out of 865 submissions)
[C41] T. Luo, D. Newmark and D. Z. Pan, "A New LP Based Incremental Timing Driven Placement for High Performance Designs", Proc.43rd ACM/IEEE Design Automation Conference (DAC), San Francisco, California, July, 2006
[C40] M. Cho and D. Z. Pan, "PEAKASO: Peak-Temperature Aware Scan-Vector Optimization", VLSI Test Symposium, Berkeley, CA (VTS), May 2006
[C39] A. Rajaram and D. Z. Pan, Variation Tolerant Buffered Clock Network Synthesis with Cross Links" , International Symposium on Physical Design (ISPD), San Francisco, CA, April 2006 (covered by EE Times on April 17, 2006 in the report "Paths to better timing analysis" by Richard Goering)
[C38] A. Havlir and D. Z. Pan, "Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines", International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2006
[C37] A. Ramalingam, F. Liu, S. R. Nassif, and D. Z. Pan, "Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity", International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2006
[C36] A. Rajaram and D. Z. Pan, "Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction", International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2006
[C35] P. Yu, D. Z. Pan and C. A. Mack, Fast Lithography Simulation under Focus Variations for OPC and Layout Optimizations", SPIE Design and Process Integration for Microelectronic Manufacturing IV, Feb. 2006
[C34] M. Cho, H. Shin and D. Z. Pan, "Fast Substrate Noise-Aware Floorplanning with Preference Directed Graph for Mixed-Signal SOCs", Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2006, (Nominated for Best Paper Award, 8 out of 424 submissions).
[C33] S. X. Shi and D. Z. Pan, "Wire Sizing and Shaping with Scattering Effect for Nanoscale Interconnection", Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2006.
[C32] A. Ramalingam, S. V. Kodakara, A. Devgan and D. Z. Pan, "Robust Analytical Gate Delay Modeling for Low Voltage Circuits", Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2006
[C31] T. Luo, H. Ren, C. Alpert and D. Z. Pan, "Computational Geometry Based Placement Migration", Proc. ACM/IEEE Int'l Conference on Computer-Aided Design (ICCAD), November, 2005
[C30] M. Cho, S. Ahmed and D. Z. Pan, "TACO: Temperature Aware Clock Optimization", Proc. ACM/IEEE Int'l Conference on Computer-Aided Design (ICCAD), November, 2005 (covered by EE Times on June 19, 2006 in the report "Chip designers feel the heat" by Richard Goering)
[C29] D. Z. Pan, "Lithography Aware Physical Design", 6th International Conf. on ASIC (ASICON), Shanghai, Oct. 24-27, 2005 (Invited Paper at the Special Session on DFM)
[C28] J. Mitra, P. Yu and D. Z. Pan, "RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations", Proc. 42nd ACM/IEEE Design Automation Conference (DAC), Anaheim, California, June, 2005.
[C27] H. Ren, D. Z. Pan, C. Alpert and P. Villarrubia, "Diffusion Based Placement Migration", Proc. 42nd ACM/IEEE Design Automation Conference (DAC), Anaheim, California, June, 2005.
[C26] D. Z. Pan and M. D. F. Wong, "Manufacturability Aware Physical Layout Optimizations", International Conference on IC Design and Technology (ICICDT), Austin, TX, May 2005 (Invited Paper)
[C25] J. Mitra and P. Yu and D. Z. Pan, "RADAR: RET-Aware Detailed Routing", Electronic Design Process (EDP) Workshop, Monterey, California, April, 2005.
[C24] H. Ren, D. Z. Pan, C. Alpert and P. Villarrubia, "Diffusion Based Placement Migration", Electronic Design Process (EDP) Workshop, Monterey, California, April, 2005.
[C23] A. Rajaram, D. Z. Pan and J. Hu, "Improved Algorithms for Link Based Non-tree Clock Network for Skew Variability Reduction", Proc. International Symposium on Physical Design (ISPD), San Francisco, CA, April 2005.
[C22] A. Ramalingam, B. Zhang, A. Devgan, and D. Z. Pan, "Sleep Transistor Sizing Using Timing Criticality and Temporal Currents", Proc. Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2005.
[C21] G. Xu, L. Huang, D. Z. Pan and M. D.-F. Wong, "Redundant-Via Enhanced Maze Routing for Yield Improvement", Proc. Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2005.
[C20] G. Xu, R. Tian, D. Z. Pan and M. D.-F. Wong, "CMP Aware Shuttle Mask Floorplanning", Proc. Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2005.
[C19] H. Ren, D. Z. Pan and P. Villarrubia, "True Crosstalk Aware Incremental Placement with Noise Map", Proc. ACM/IEEE Int'l Conference on Computer-Aided Design (ICCAD), November, 2004.
[C18] G. Xu, R. Tian, D. Z. Pan and M. D.F. Wong, "A Multi-objective Floorplanner for Shuttle Mask Optimization", Proc. SPIE International Symp. on Photomask Technology, Sept. 2004
[C17] H. Ren, D. Z. Pan and D. S. Kung, "Sensitivity Guided Netweighting for Placement Driven Synthesis", Proc. International Symposium on Physical Design (ISPD), Phoenix, Arizona, April 2004
[C16] R. Puri, L. Stok, J. Cohn, D. Kung, D. Z. Pan, D. Sylvester, A. Srivastava, and S. H. Kulkarni, "Pushing ASIC Performance in a Power Envelope", Proc. 40th ACM/IEEE Design Automation Conference (DAC), Anaheim, California, June, 2003.
[C15] D. Z. Pan, A. Correale, D. Lamb, D. Wallach, D. Kung, and R. Puri, "Generic Voltage Island: CAD Flow and Design Experience", Austin Conference on Energy Efficient Design (ACEED), Austin, Texas, Feb, 2003.
[C14] R. Puri, D. Z. Pan and D. Kung, "A Flexible Design Approach for the Use of Dual Supply Voltages and Level Conversion for Low-Power ASIC Design", Austin Conference on Energy Efficient Design (ACEED), Austin, Texas, Feb, 2003.
[C13] C.-C. Chang, J. Cong, D. Z. Pan and X. Yuan, "Physical Hierarchy Generation with Routing Congestion and Control", Proc. International Symposium on Physical Design (ISPD), pp36-41, San Diego, California, April 2002.
[C12] J. Cong, D. Z. Pan and P.V. Srinivas, "Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization", Proc. Asia South Pacific Design Automation Conference (ASPDAC), Jan. 30 - Feb. 2, 2001, Pacifico Yokohama, Japan.
[C11] J. Cong, D. Z. Pan and P.V. Srinivas, "Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization", Proc. ACM/ACM TAU, Dec. 4-5, 2000, Austin.
[C10] C.-C. Chang, J. Cong, D. Z. Pan and X. Yuan, " Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization", Proc. SRC Techcon Conference, September 21-3, 2000, Phoenix,
[C9] J. Cong, D. Z. Pan and P.V. Srinivas, " Improved Crosstalk Modeling with Applications to Noise Constrained Interconnect Optimization", Proc. SRC Techcon Conference, September 21-3, 2000, Phoenix
[C8] J. Cong, T. Kong and D. Z. Pan, "Buffer Block Planning for Interconnect-Driven Floorplanning", Proc. ACM/IEEE Int'l Conference on Computer-Aided Design (ICCAD) , November, 1999.
[C7] J. Cong and D. Z. Pan, "Interconnect Estimation and Planning for Deep Submicron Designs", Proc. ACM/IEEE 36th Design Automation Conference (DAC) , June 20-5, 1999, New Orleans.
[C6] J. Cong and D. Z. Pan, "Interconnect Delay and Area Estimation for Multiple-Pin Nets", Proc. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 8-9, 1999, Monterey.
[C5] J. Cong and D. Z. Pan, "Interconnect Delay Estimation Models for Synthesis and Design Planning", Proc. Asian and South Pacific Design Automation Conference (ASPDAC), January 18-21, 1999, Hong Kong.
[C4] J. Cong and D. Z. Pan, "Interconnect Delay Estimation Models for Logic and High Level Synthesis", Proc. SRC Techcon Conference, September 9-11, 1998, Las Vegas. (Best Paper in Session Award)
[C3] J. Cong and D. Z. Pan, " Interconnect Performance Estimation Models for Synthesis and Design Planning", ACM/IEEE Int'l Workshop on Logic Synthesis, June, 1998.
[C2] J. Cong, L. He, C.-K. Koh and Z. Pan, "Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance", Proc. ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November, 1997.
[C1] J. Cong, L. He, K.-Y. Khoo, C.-K. Koh and Z. Pan, "Interconnect Design for Deep Submicron ICs", Proc. ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November, 1997. (Embedded Tutorial)
JOURNAL ARTICLES PAPERS (Go to Top)
[J14] Minsik Cho and David Z. Pan, "A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , (accepted)[J13] David Z. Pan, Peng Yu, Minsik Cho, Anand Ramalingam, Kiwoon Kim, Anand Rajaram and Sean X. Shi, "Design for Manufacturing Meets Advanced Process Control: A Survey", Journal of Process Control, (accepted)
[J12] Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "TROY: Track Routing and Optimization for Yield", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , (accepted)
[J11] M. Cho and D. Z. Pan, "Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs", IEEE Transactions on VLSI Systems, (accepted)
[J10] H. Ren, D. Z. Pan, C. J. Alpert, P. Villarrubia, and G.-J. Nam, "Diffusion-Based Placement Migration with Application on Legalization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 26, Issue 12, pp. 2158-2172, December 2007
[J9] M. Cho and D. Z. Pan, "BoxRouter: A New Global Router Based on Box Expansion", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 26, Issue 12, pp. 2130-2143, December 2007
[J8] P. Yu, S. X. Shi, and D. Z. Pan, "True Process Variation Aware Optical Proximity Correction with Variational Lithography Modeling and Model Calibration", The Journal of Microlithography, Microfabrication, and Microsystems (JM3), Special Edition of Resolution Enhancement Techniques and Design for Manufacturability, September 2007
[J7] A. Ramalingam, A. Devgan, and D. Z. Pan, "Wakeup Scheduling in MTCMOS Circuits using Successive Relaxation to Minimize Ground Bounce", ASP Journal of Low Power Electronics (JOLP), Vol 3, No. 1, April 2007
[J6] H. Ren, D. Z. Pan and D. S. Kung, "Sensitivity Guided Netweighting for Placement Driven Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May, 2005.
[J5] C.-C. Chang, J. Cong, D. Z. Pan and X. Yuan, "Multilevel Global Placement with Congestion Control", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 4, pp.395-409, April 2003.
[J4] J. Cong and D. Z. Pan, "Wire Width Planning for Interconnect Performance Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 3, pp.319-329, March 2002.
[J3] J. Cong, T. Kong and D. Z. Pan, "Buffer Block Planning for Interconnect Planning and Prediction", IEEE Transactions on VLSI Systems , vol. 9, no. 6, pp.929-937, December 2001.
[J2] J. Cong, L. He, C.-K. Koh and D. Z. Pan, "Interconnect Sizing and Spacing with Consideration of Coupling Capacitance", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp.1164-1169, September 2001.
[J1] J. Cong and D. Z. Pan, "Interconnect Performance Estimation Models for Design Planning" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 739--752, vol. 20, no. 6, June 2001
PATENTS (Go to Top)
[P5] Jason Cong and Zhigang Pan, "Wire Width Planning and Performance Optimization for VLSI Interconnects, U.S. Patent No. 6,408,427[P4] Jason Cong, Zhigang Pan, and P.V. Srinivas, "Method and Apparatus for Calculation of Crosstalk Noise in Integrated Circuits", U.S. Patent, No. 7,013,253. Granted March 2006.
[P3] Anthony Correale, Jr., David S. Kung, Zhigang Pan, Ruchir Puri, "Method and Program Product of Level Converter Optimization", U.S. Patent, No. 7,089,510, Granted on August 8, 2006.
[P2] Anthony Correale, Jr., David S. Kung, Douglas T. Lamb, Zhigang Pan, Ruchir Puri, David Wallach, "Multiple Voltage Integrated Circuit and Design Method Therefor", US Patent, No. 7,111,266, Granted on Sept. 19, 2006.
[P1] Anthony Correale, Jr., Rajeev Joshi, David S. Kung, Zhigang Pan, Ruchir Puri, "Single Supply Level Converter". US Patent, No. 7,119,578. Granted on Oct. 10, 2006.
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