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Disclaimer: Many papers below have been made available in PDF format for easy access. However, please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.
Jump to -    Books/Books Chapters     Conference Papers     Journal Articles      Patents

BOOKS / BOOK CHAPTERS (Go to Top)


[B9] Meng Li and David Z. Pan,"A Synergistic Framework for Hardware IP Privacy and Integrity Protection," Springer, 2020 Edition

[B8] Yibo Lin and David Z. Pan,"Machine Learning in Physical Verification, Mask Synthesis, and Physical Design," in Machine Learning in VLSI Computer-Aided Design (edited by Elfadel I., Boning D., Li X.) Springer, 2019 Edition

[B7] Bei Yu and David Z. Pan,"Design for Manufacturability with Advanced Lithography," Springer, 2016 Edition

[B6] Bei Yu and David Z. Pan,"Layout Decomposition for Triple Patterning" in Encyclopedia of Algorithms (edited by M.-Y. Kao eds.), Springer, 2015 Edition

[B5] Minsik Cho and David Z. Pan,"Global Routing" in Encyclopedia of Algorithms (edited by M.-Y. Kao eds.), Springer, 2015 Edition

[B4] D. Z. Pan and M. Stan,"Physical Design and Interaction with Technology" in CAD Algorithms, Methods and Tools For Low-Power Circuits and Systems (edited by Enrico Macii), Jan. 2006 (IEEE Technology Survey)

[B3] D. Z. Pan, B. Halpin, and H. Ren,"Timing-Driven Placement" in Handbook of Algorithms for VLSI Physical Automation (edited by Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar), CRC Press, 2007 (Invited) (Amazon) (ISBN: 0849372429)

[B2] T. Luo and D. Z. Pan,"DPlace: Anchor Cell based Quadratic Placement with Linear Objective" in Modern Circuit Placement: Best Practices and Results (edited by Gi-Joon Nam and Jason Cong), Springer, 2007 (Invited) (Amazon) (ISBN: 038736837X)

[B1] M. Cho, J. Mitra, and D. Z. Pan,"Manufacturability Aware Routing" in Handbook of Algorithms for VLSI Physical Automation (edited by Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar), CRC Press, 2007 (Invited) (Amazon) (ISBN: 0849372429)


CONFERENCE PAPERS (Go to Top)

[C345] Souradip Poddar, Ahmet Budak, Linran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu, Yaoyao Jia, and David Z. Pan, “A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing,” IEEE/ACM Design, Automation and Test in Europe (DATE), Valencia, Spain, March 25-27, 2024. (Accepted).

[C344] Supriyo Maji, Sungyoung Lee, and David Z. Pan, “Analog Transistor Placement Optimization Considering Non-Linear Spatial Variation,” IEEE/ACM Design, Automation and Test in Europe (DATE), Valencia, Spain, March 25-27, 2024. (Accepted).

[C343] Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen and Xiaoqing Xu, “ISDC: Feedback-guided Iterative SDC Scheduling for High-evel Synthesis,” IEEE/ACM Design, Automation and Test in Europe (DATE), Valencia, Spain, March 25-27, 2024. (Accepted).

[C342] Hanqing Zhu, Jiaqi Gu, Hanrui Wang, Zixuan Jiang, Rongxing Tang, Zhekai Zhang, Chenghao Feng, Song Han, Ray T. Chen, and David Z. Pan, "Lightening-Transformer: A Dynamically Operated Optically-Interconnected Photonic Transformer Accelerator," IEEE International Symposium on High-Performance Computer Architecture (HPCA), Edinburgh, Scotland, UK, Mar 2 - Mar 6, 2024. (Accepted).

[C341] Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel de Araujo, Doug Wallace, Doug Winterberg, Adam Klivans and David Z. Pan, "ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning," IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Incheon, S. Korea, Jan 22-25, 2024 (Accepted).

[C340] Chen-Hao Hsu, Xiaoqing Xu, Hao Chen, Dino Ruic, and David Z. Pan, “TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Incheon, S. Korea, Jan 22-25, 2024.

[C339] Ahmet Budak, Keren Zhu, and David Pan, “Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, Oct. 30 - Nov. 3, 2023.

[C338] Hyunsu Chae, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Arun Chada, Adam Klivans, and David Z. Pan, "Method of Exploring HVM Process Corner Cases for Loss and Impedance in High Speed Designs," IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Milpitas, CA, Oct. 15-18, 2023 (Accepted).

[C337] Tianlong Chen, Zhenyu Zhang, Hanrui Wang, Jiaqi Gu, Zirui Li, David Z. Pan, Frederic Chong, Song Han, and Zhangyang Wang, “QuantumSEA: In-Time Sparse Exploration for Noise Adaptive Quantum Circuits,” IEEE International Conference on Quantum Computing and Engineering (QCE), Sep 17 - Sep 22, 2023.

[C336] Zixuan Jiang, Jiaqi Gu, and David Z. Pan, “NormSoftmax: Normalizing the Input of Softmax to Accelerate and Stabilize Training,” IEEE International Conference on Omni-layer Intelligent Systems (COINS), Hybrid (virtual and Berlin, Germany), July 23 - 25, 2023.

[C335] Zixuan Jiang, Jiaqi Gu, Mingjie Liu, and David Z. Pan, “Delving into Effective Gradient Matching for Dataset Condensation,” IEEE International Conference on Omni-layer Intelligent Systems (COINS), Hybrid (virtual and Berlin, Germany), July 23 - 25, 2023.

[C334] Hanqing Zhu, Jiaqi Gu, Hanrui Wang, Rongxing Tang, Zhekai Zhang, Chenghao Feng, Song Han, Ray T. Chen and David Z. Pan, “DOTA: A Dynamically-Operated Photonic Tensor Core for Energy-Efficient Transformer Accelerator,” Systems for Next-Gen AI Paradigms (SNAP) Workshop @ Conference on Machine Learning and Systems (MLSys), Miami, OL, June 4 - 8, 2023.

[C333] Jiaqi Gu, Chenghao Feng, Hanqing Zhu, Ray T. Chen, and David Z. Pan, “Light-AI Interaction: Bridging Photonics and AI with Cross-Layer Hardware-Software Co-Design,” Systems for Next-Gen AI Paradigms (SNAP) Workshop @ Conference on Machine Learning and Systems (MLSys), Miami, OL, June 4 - 8, 2023.

[C332] Chenghao Feng, Jiaqi Gu, Hanqing Zhu, Rongxing Tang, David Z. Pan, and Ray T. Chen, “Evaluation of a compact butterfly-style photonic-electronic neural chip on complicated deep learning tasks,” Conference on Lasers and Electro-Optics (CLEO), San Jose, CA, May 07-12, 2023.

[C331] Hyunsu Chae, Bhyrav Mutnury, Keren Zhu, Doug Wallace, Doug Winterberg, Daniel de Araujo, Jay Reddy, Adam Klivans and David Z. Pan, "ISOP: Machine Learning Assisted Inverse Stack-Up Optimization for Advanced Package Design," IEEE/ACM Design, Automation and Test in Europe (DATE), Apr. 17 - Apr. 19, 2023.

[C330] Ahmet F. Budak, Keren Zhu, Hao Chen, Souradip Poddar, Linran Zhao, Yaoyao Jia, and David Z. Pan, “Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities,” ACM International Symposium on Physical Design (ISPD), 2023. (Invited Paper)

[C329] Rachel Selina Rajarathnam, Zixuan Jiang, Mahesh A. Iyer, and David Z. Pan, "DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs," ACM International Symposium on Physical Design (ISPD), 2023.

[C328] Hao Chen, Kai-Chieh Hsu, Walker Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, and Haoxing Ren, "Reinforcement Learning Guided Detailed Routing for Custom Circuits," ACM International Symposium on Physical Design (ISPD), 2023.

[C327] Jiaqi Gu, Chenghao Feng, Hanqing Zhu, Ray T. Chen, and David Z. Pan, “Light-AI Interaction: The Convergence of Photonic AI and Cross-layer Circuit-Architecture-Algorithm Co-design,” SPIE Photonics West (OPTO), San Francisco, CA, Jan 28 - Feb 2, 2023 (Invited Paper)

[C326] Chenghao Feng, Rongxing Tang, Jiaqi Gu, Hanqing Zhu, David Z. Pan, and Ray T. Chen, “Optically-Interconnected, Hardware-Efficient, Electronic-Photonic Neural Network using Compact Multi-Operand Photonic Devices,” SPIE Photonics West (OPTO)i>, San Francisco, CA, Jan 28 -Feb 2, 2023

[C325] Ahmet F. Budak, David Smart, Brian Swahn and David Z. Pan, "APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors using DNN Learning," IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan. 16-19, 2023.

[C324] Jiaqi Gu, Ben Keller, Jean Kossaifi, Anima Anandkumar, Brucek Khailany, David Z. Pan, "HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression," Conference on Neural Information Processing Systems (NeurIPS), ML for System Workshop,, Nov. 26 - Dec. 4, 2022.

[C323] Jiaqi Gu, Zhengqi Gao, Chenghao Feng, Hanqing Zhu, Ray Chen, Duane S Boning and David Z. Pan, "NeurOLight: A Physics-Agnostic Neural Operator Enabling Parametric Photonic Device Simulation," Conference on Neural Information Processing Systems (NeurIPS), Nov. 26 - Dec. 4, 2022.

[C322] Hanrui Wang, Pengyu Liu, Jinglei Cheng, Zhiding Liang, Jiaqi Gu, Zirui Li, Yongshan Ding, Weiwen Jiang, Yiyu Shi, Xuehai Qian, David Z. Pan, Frederic T. Chong and Song Han, "Graph Transformer for Quantum Circuit Reliability Prediction," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, Oct. 30–Nov. 3, 2022.

[C321] Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray Chen, Jean Anne Incorvia, and David Z. Pan, "Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, Oct. 30–Nov. 3, 2022.

[C320] Keren Zhu, Hao Chen, Walker Turner, George Kokai, Po-Hsuan Wei, David Z. Pan, and Haoxing Ren, "TAG: Learning Circuit Spatial Embedding From Layouts," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, Oct. 30–Nov. 3, 2022.

[C319] Zixuan Jiang, Mingjie Liu, Zizheng Guo, Shuhan Zhang, Yibo Lin, and David Z. Pan, “A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation,” ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Snowbird, Utah, Sept. 12-13, 2022.

[C318] Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Mingjie Liu, Shuhan Zhang, Ray T. Chen, and David Z. Pan, "ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Jul. 10-14, 2022.

[C317] Hanrui Wang, Zirui Li, Jiaqi Gu, Yongshan Ding, David Z. Pan, and Song Han, "On-Chip QNN: Towards Efficient On-Chip Training of Quantum Neural Networks," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Jul. 10-14, 2022.

[C316] Hanrui Wang, Jiaqi Gu, Yongshan Ding, Zirui Li, Frederic T. Chong, David Z. Pan, and Song Han, "RobustQNN: Noise-Aware Training for Robust Quantum Neural Networks," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Jul. 10-14, 2022.

[C315] Zizheng Guo*, Mingjie Liu*, Jiaqi Gu, Shuhan Zhang, David Z. Pan, and Yibo Lin, "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Jul. 10-14, 2022. (* indicates equal contributions)

[C314] Venkata Suresh Rayudu, Ki Yong Kim, David Z. Pan, and Ranjit Gharpurey, "A Feedback-Based N-Path Receiver with Reduced Input-Node Harmonic Response," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Denver, CO, Jun. 19-21, 2022.

[C313] Jiaqi Gu, Hyoukjun Kwon, Dilin Wang, Wei Ye, Meng Li, Yu-Hsin Chen, Liangzhen Lai, Vikas Chandra, and David Z. Pan, "Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation," IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), New Orleans, Louisiana, Jun. 21-24, 2022.

[C312] Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, and Haoxing Ren "AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies," ACM International Symposium on Physical Design (ISPD), Virtual Event, Canada, Mar. 27-30, 2022.

[C311] Hao Chen, Walker J. Turner, David Z. Pan, and Haoxing Ren, "Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories," IEEE/ACM Design, Automation and Test in Europe (DATE), Mar. 14-23, 2022.

[C310] Chenghao Feng, Jiaqi Gu, Hanqing Zhu, Zhoufeng Ying, Zheng Zhao, David Z. Pan, and Ray T. Chen, "Optoelectronically Interconnected Hardware-Efficient Deep Learning using Silicon Photonic Chips," SPIE PC12007, Optical Interconnects XXII,, San Francisco, CA, Mar 5, 2022.

[C309] Chenghao Feng, Jiaqi Gu, Hanqing Zhu, David Z. Pan, and Ray T. Chen, "Design and Experimental Demonstration of A Hardware-Efficient Integrated Optical Neural Network," SPIE PC12007, Optical Interconnects XXII,, San Francisco, CA, Mar 5, 2022.

[C308] Hanrui Wang, Yongshan Ding, Jiaqi Gu, Yujun Lin, David Z. Pan, Fred Chong, Song Han, "QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits," The 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA-28) (HPCA 2022) , Feb. 12-16, 2022.

[C307] Keren Zhu, Hao Chen, Mingjie Liu, and David Z. Pan, "Automating Analog Constraint Extraction: From Heuristics to Learning," IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Jan. 17-20, 2022. (Invited Paper)

[C306] Ahmet F. Budak*, Zixuan Jiang*, Keren Zhu, Azalia Mirhoseini, Anna Goldie, and David Z. Pan, "Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives," IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Jan. 17-20, 2022. (Invited Paper) (* equal contributions in alphabetic order)

[C305] Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun and David Z. Pan, "Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits," IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Jan. 17-20, 2022.

[C304] Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh Iyer and David Z. Pan, "DREAMPlaceFPGA: an open-source analytical placer for large scale heterogeneous fpgas using deep-learning toolkit," IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Jan. 17-20, 2022.

[C303] Hanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen and David Z. Pan, "ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement," IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Jan. 17-20, 2022.

[C302] Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Ray T. Chen, and David Z. Pan, "L2ight: Enabling On-Chip Learning for Optical Neural Networks via Efficient in-situ Subspace Optimization," Conference on Neural Information Processing Systems (NeurIPS), Dec. 7-10, 2021.

[C301] Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun and David Z. Pan, "OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 1-4, 2021.

[C300] Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, and David Z. Pan, "Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation," International Conference on Computer Vision (ICCV), Oct. 10-17, 2021.

[C299] Zixuan Jiang, Ebrahim Songhori, Shen Wang, Anna Goldie, Azalia Mirhoseini, Joe Jiang, Young-Joon Lee and David Z. Pan, "Delving into Macro Placement with Reinforcement Learning," ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Aug. 31 – Sept. 2, 2021.

[C298] Mohamed Baker Alaweih and David Z. Pan, "ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection," ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Aug. 31 – Sept. 2, 2021.

[C297] Chenghao Feng, Jiaqi Gu, Hanqing Zhu, David Z. Pan, and Ray T. Chen, "Experimental Demonstration of a WDM-based Integrated Optical Decoder for Compact Optical Computing", Conference on Lasers and Electro-Optics, May 2021.

[C296] Jason Midkiff, Ali Rostamian, Kyoung Min Yoo, Aref Asghari, Chao Wang, Chenghao Feng, Zhoufeng Ying, Jiaqi Gu, Haixia Mei, Ching-Wen Chang, James Fang, Alan Huang, Jong-Dug Shin, Xiaochuan Xu, Michael Bukshtab, David Z. Pan, and Ray T. Chen, "Integrated Photonics for Computing, Interconnects and Sensing", Conference on Lasers and Electro-Optics, May 2021. (Invited Paper)

[C295] Chenghao Feng, Jiaqi Gu, Zhoufeng Ying, Zheng Zhao, David Z. Pan, Ray T. Chen, "Scalable fast-Fourier-transform-based (FFT-based) integrated optical neural network for compact and energy-efficient deep learning", Proc. SPIE 11690, Smart Photonic and Optoelectronic Integrated Circuits XXIII, 116900R, March 2021.

[C294] Chenghao Feng, Zhoufeng Ying, Zheng Zhao, Jiaqi Gu, David Z. Pan, Ray T. Chen, "Wavelength-division-multiplexing-based electronic-photonic integrated circuits for high-performance data processing and transportation", Proc. SPIE 11690, Smart Photonic and Optoelectronic Integrated Circuits XXIII, 116900R, March 2021.

[C293] Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Junior, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, et al., "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization", IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Feb. 2021.

[C292] Mario Miscuglio, Zibo Hu, Shurui Li, Jiaqi Gu, Aydin Babakhani, Puneet Gupta, Chee-Wei Wong, David Z. Pan, Seth Bank, Hamed Dalir, and Volker J. Sorger, "Massive parallelism Fourier-optic convolutional processor", Signal Processing in Photonic Communications (SPPCom), July 2020.

[C291] Mario Miscuglio, Zibo Hu, Shurui Li, Jiaqi Gu, Aydin Babakhani, Puneet Gupta, Chee-Wei Wong, Hamed Dalir, David Z. Pan, Seth Bank, and Volker J. Sorger, "Million-channel parallelism Fourier-optic convolutional filter and neural network processor", Conference on Lasers and Electro-Optics, 2020.

[C290] Xiaohan Gao, Mingjie Liu, David Z. Pan and Yibo Lin, "Interactive Analog Layout Editing with Instant Placement Legalization", ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 11-15, 2021.

[C289] Ahmet F. Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan and Chandramouli V. Kashyap, "DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks", ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Dec. 5-9, 2021.

[C288] Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, and David Z. Pan, "Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks", ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Dec. 5-9, 2021.

[C287] Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu and Nan Sun, "An In-Memory-Computing Charge-Domain Ternary CNN Classifier," IEEE Custom Integrated Circuits Conference (CICC),, April 25-30, 2021.

[C286] Hao Chen*, Mingjie Liu*, Xiyuan Tang*, Keren Zhu*, Abhishek Mukherjee, Nan Sun and David Z. Pan, "MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1 GS/s \Delta\SigmaM ADC," IEEE Custom Integrated Circuits Conference (CICC),, April 25-30, 2021. (* equal contributions in alphabetic order)

[C285] Jiaqi Gu, Chenghao Feng, Zheng Zhao, Zhoufeng Ying, Ray T. Chen and David Z. Pan, "Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization," Association for the Advancement of Artificial Intelligence (AAAI),, Feb. 2-9, 2021.

[C284] Jiaqi Gu, Chenghao Feng, Zheng Zhao, Zhoufeng Ying, Mingjie Liu, Ray T. Chen and David Z. Pan, "SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators," IEEE Design, Automation & Test in Europe (DATE) Conference, Feb. 1-5, 2021.

[C283] Jiaqi Gu, Zheng Zhao, Chenghao Feng, Zhoufeng Ying, Ray T. Chen and David Z. Pan, "O2NN: Optical Neural Networks with Differential Detection-Enabled Optical Operands," IEEE Design, Automation & Test in Europe (DATE) Conference, Feb. 1-5, 2021.

[C282] Mingjie Liu, Walker Turner, George Kokai, Brucek Khailany, David Z. Pan and Haoxing Ren, "Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization," IEEE Design, Automation & Test in Europe (DATE) Conference, Feb. 1-5, 2021.

[C281] Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, and Nan Sun, "A 0.4-to-40MS/s 75.7dB-SNDR Fully-Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier," IEEE International Solid-State Circuits Conference (ISSCC), Feb, 2021.

[C280] Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan and Yibo Lin, "Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks," IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan 18-21, 2021.

[C279] Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao and David Z. Pan, "Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network," ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), November 16-20, 2020.

[C278] Mohamed Baker Alawieh, Wei Ye and David Z. Pan, "Re-examining VLSI Manufacturing and Yield through the Lens of Deep Learning," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 02-05, 2020. (Invited Paper)

[C277] Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun and David Z. Pan, "Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 02-05, 2020.

[C276] Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun and David Z. Pan, "Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 02-05, 2020.

[C275] Jiaqi Gu, Zixuan Jiang, Yibo Lin and David Z. Pan, "DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 02-05, 2020.

[C274] Zixuan Jiang, Keren Zhu, Mingjie Liu, Jiaqi Gu and David Z. Pan, "An Efficient Training Framework for Reversible Neural Architectures," European Conference on Computer Vision (ECCV), Glasgow, United Kingdom, August 23-27, 2020.

[C273] Jiaqi Gu, Zheng Zhao, Chenghao Feng, Wuxi Li, Ray T. Chen and David Z. Pan, "FLOPS: Efficient On-Chip Learning for Optical Neural Networks Through Stochastic Zeroth-Order Optimization," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020. (Best Paper Award Nomination)

[C272] Navid Khoshavi, Arman Roohi, Connor Broyles, Saman Sargolzaei, Yu Bi and David Z. Pan, "SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020.

[C271] Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun and David Z. Pan, "Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020.

[C270] Mohamed Baker Alawieh, Duane Boning and David Z. Pan, "Wafer Map Detect Patterns Classification using Deep Selective Learning," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020.

[C269] Rachel Selina Rajarathnam, Yibo Lin, Yier Jin and David Z. Pan, "ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist," IEEE International Symposium on Hardware Oriented Security and Trust (HOST), San Jose, CA, May 4-7, 2020.

[C268] Wei Ye, Mohamed Baker Alawieh, Yuki Watanabe, Shigeki Nojima, Yibo Lin and David Z. Pan, "TEMPO: Fast Mask Topography Effect Modeling with Deep Learning," ACM International Symposium on Physical Design (ISPD), Taipei, Taiwan, Mar 29-Apr 1, 2020. (Best Paper Award)

[C267] Mingjie Liu*, Keren Zhu*, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun and David Z. Pan, "Towards Decrypting the Art of Analog Layout, Placement Quality Prediction via Transfer Learning," IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, Mar. 09-13, 2020. (* indicates equal contributions)

[C266] Jiaqi Gu, Zheng Zhao, Chenghao Feng, Hanqing Zhu, Ray T. Chen, David Z. Pan, "ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls," IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, Mar. 09-13, 2020.

[C265] Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan and Nan Sun, "A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 16-20, 2020.

[C264] Jiaqi Gu, Zheng Zhao, Chenghao Feng, Mingjie Liu, Ray T. Chen, David Z. Pan, "Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Beijing, China, Jan. 13-16, 2020. (Best Paper Award)

[C263] Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun and David Z. Pan, "S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Beijing, China, Jan. 13-16, 2020. (Best Paper Award Nomination)

[C262] Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh Iyer and David Z. Pan, "High-Definition Routing Congestion Prediction for Large-Scale FPGAs," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Beijing, China, Jan. 13-16, 2020.

[C261] Zheng Zhao, Jiaqi Gu, Zhoufeng Ying, Chenghao Feng, Ray T. Chen and David Z. Pan, "Design Technology for Scalable and Robust Photonic Integrated Circuits," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, Nov. 4-7, 2019. (Invited Paper)

[C260] Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, and David Z. Pan, "MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, Nov. 4-7, 2019. (Invited Paper)

[C259] Kaveh Shamsi, David Z. Pan and Yier Jin, "IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, Nov. 4-7, 2019.

[C258] Chengyue Gong*, Zixuan Jiang*, Dilin Wang, Yibo Lin, Qiang Liu, David Z. Pan, "Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, Nov. 4-7, 2019. (* indicates equal contributions)

[C257] Wuxi Li, Yibo Lin and David Z. Pan, "elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, Nov. 4-7, 2019.

[C256] Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun and David Z. Pan, "GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, Nov. 4-7, 2019.

[C255] Shounak Dhar, Love Singhal, Mahesh A. Iyer and David Z. Pan, "FPGA-Accelerated Spreading for Global Placement," IEEE High Performance Extreme Computing Conference (HPEC), Waltham, WA, Sep. 24-26, 2019.

[C254] Shounak Dhar, Love Singhal, Mahesh A. Iyer and David Z. Pan, "FPGA Accelerated FPGA Placement," International Conference on Field-Programmable Logic and Applications (FPL), Barcelona, Spain, Sep. 9-13, 2019.

[C253] Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun and David Z. Pan, "WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout," ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, Jun. 2-6, 2019.

[C252] Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany and David Z. Pan, "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement," ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, Jun. 2-6, 2019. (Best Paper Award)

[C251] Wei Ye, Mohamed Baker Alawieh, Yibo Lin, and David Z. Pan, "LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks," ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, Jun. 2-6, 2019. (Best Paper Award Nomination)

[C250] Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang and David Z. Pan, "GAN-SRAF: Sub-Resolution Assist Feature Generation using Conditional Generative Adversarial Networks," ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, Jun. 2-6, 2019.

[C249] Mohamed Baker Alawieh, Sinead Williamson and David Z. Pan, "Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab Models," ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, Jun. 2-6, 2019.

[C248] Kaveh Shamsi, David Z. Pan and Yier Jin, "On the Impossibility of Approximation-Resilient Circuit Locking," IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Tysons Corner, USA, May 6 - 10, 2019.

[C247] Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan and Nan Sun, "A 0.025mm2 0.8V 78.5dB SNDR VCO-based Sensor Readout Circuit Using a Hybrid PLL-\Delta\SigmaM Structure,", IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr. 14-17, 2019.

[C246] Shaolan Li, Biying Xu, David Z. Pan and Nan Sun, "A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library,", IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr. 14-17, 2019.

[C245] Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun and David Z. Pan, "Device Layer-Aware Analytical Placement for Analog Circuits," ACM International Symposium on Physical Design (ISPD), San Francisco, CA, Apr. 14-17, 2019. (Best Paper Award Nomination)

[C244] Kaveh Shamsi, Meng Li, David Z. Pan and Yier Jin, "Key-Condition Crunching for Fast Sequential Circuit Deobfuscation," IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, March 25-29, 2019.

[C243] Wei Ye, Mohamed Baker Alawieh, Meng Li, Yibo Lin, and David Z. Pan, "Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection," IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, March 25-29, 2019.

[C242] Zheng Zhao, Derong Liu, Zhoufeng Ying, Biying Xu, Chenghao Feng, Ray T. Chen. and David Z. Pan, "Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis," IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, March 25-29, 2019.

[C241] Wuxi Li, Mehrdad Eslami Dehkordi, Stephen Yang and David Z. Pan, "Simultaneous Placement and Clock Tree Construction for Modern FPGAs," ACM International Symposium on Field-Programmable Gate Arrays (FPGA), Seaside, CA, February 24 - 26, 2019.

[C240] Wei Ye, Yibo Lin, Meng Li, Qiang Liu, and David Z. Pan, "LithoROC: Lithography Hotspot Detection with Explicit ROC Optimization," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Jan. 21–24, 2019. (Invited Paper)

[C239] Shounak Dhar, Love Singhal, Mahesh A. Iyer, and David Z. Pan, "A Shape-Driven Spreading Algorithm Using Linear Programming for Global Placement," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Jan. 21–24, 2019.

[C238] Wei Ye, Mohamed Baker Alawieh, Yibo Lin, and David Z. Pan, "Tackling Signal Electromigration with Learning-Based Detection and Multistage Mitigation," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Jan. 21–24, 2019.

[C237] Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, and David Z. Pan, "Semi-Supervised Hotspot Detection with Self-Paced Multi-Task Learning," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Jan. 21–24, 2019.

[C236] Mohamed Baker Alawieh, Xiyuan Tang and David Z. Pan, "S2-PM: Semi-Supervised Learning for Efficient Performance Modeling of Analog and Mixed Signal Circuits," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Jan. 21–24, 2019.

[C235] Zheng Zhao, Derong Liu, Meng Li, Zhoufeng Ying, Biying Xu, Lu Zhang, Bei Yu, Ray T. Chen, and David Z. Pan, "Hardware-software Co-design of Slimmed Optical Neural Networks," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Jan. 21–24, 2019.

[C234] Yibo Lin, Mohamed Baker Alawieh, Wei Ye, and David Z. Pan, "Machine Learning for Yield Learning and Optimization," IEEE International Testing Conference, Phoenix, AZ, USA, Oct 28 - Nov 2, 2018. (Invited Paper)

[C233] Meng Li, Kaveh Shamsi, Yier Jin, and David Z. Pan, "TimingSAT: Decamouflaging Timing-based Logic Obfuscation," IEEE International Testing Conference, Phoenix, AZ, USA, Oct 28 - Nov 2, 2018.

[C232] Shounak Dhar and David Z. Pan, "GDP: GPU accelerated Detailed Placement," IEEE High Performance Extreme Computing Conference (HPEC), Boston, MA, USA, Sep. 25–27, 2018.

[C231] Derong Liu, Zheng Zhao, Zheng Wang, Zhoufeng Ying, Ray T. Chen, and David Z. Pan, "OPERON: Optical-electrical Power-efficient Route Synthesis for On-chip Signals," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Jun. 24-29, 2018.

[C230] Kaveh Shamsi, Meng Li, David Z. Pan and Yier Jin, "Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures," ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, IL, USA, May 23-25, 2018. (Best Paper Award)

[C229] Biying Xu, Bulent Basaran, Ming Su, and David Z. Pan, "Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting," ACM International Symposium on Physical Design (ISPD), Monterey, CA, Mar 25-28, 2018.

[C228] Yibo Lin, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, Meng Li, and David Z. Pan, "Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning," ACM International Symposium on Physical Design (ISPD), Monterey, CA, Mar 25-28, 2018.

[C227] Wei Ye, Meng Li, Kai Zhong, Bei Yu, and David Z. Pan, "Power Grid Reduction by Sparse Convex Optimization," ACM International Symposium on Physical Design (ISPD), Monterey, CA, Mar. 25–28, 2018.

[C226] Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan and Ulf Schlichtmann, "TimingCamouflage: Improving Circuit Security against Counterfeiting by Unconventional Timing," IEEE/ACM Design, Automation & Test in Europe (DATE), Dresden, Germany, March 2018.

[C225] Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, and David Z. Pan, "Layout-Dependent Aging Mitigation for Critical Path Timing," Asia and South Pacific Design Automation Conference (ASPDAC), Jeju, Korea, Jan. 22-25, 2018.

[C224] Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, and David Z. Pan, "A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion," Asia and South Pacific Design Automation Conference (ASPDAC), Jeju, Korea, Jan. 22-25, 2018.

[C223] Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, and David Z. Pan, "Logic Synthesis for Energy-Efficient Photonic Integrated Circuits," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Jeju, Korea, Jan. 22-25, 2018.

[C222] Zheng Wang, Zhoufeng Ying, Shounak Dhar, Zheng Zhao, David Z. Pan, and Ray T. Chen, "Optical switches based carry-ripple adder for future high-speed and low-power consumption optical computing," In CLEO: Science and Innovations, pp. STh1N-2. Optical Society of America, 2017.

[C221] Zhoufeng Ying, Zheng Wang, Shounak Dhar, Zheng Zhao, David Z. Pan, and Ray T. Chen, "On-chip Microring Resonator Based Electro-optic Full Adder for Optical Computing," In CLEO: QELS_Fundamental Science, pp. JW2A-147. Optical Society of America, 2017.

[C220] Zheng Wang, Zhoufeng Ying, Shounak Dhar, Zheng Zhao, David Z. Pan, and Ray T. Chen, "Nanophotonic devices for power-efficient computing and optical interconnects," In Photonics Society Summer Topical Meeting Series (SUM), 2017 IEEE, pp. 7-8. IEEE, 2017. (Invited Paper)

[C219] Wuxi Li, Meng Li, Jiajun Wang, and David Z. Pan, "UTPlaceF 3.0: A Parallelization Framework for Modern FPGA Global Placement," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Irvine, CA, Nov. 13-16, 2017. (Invited Paper)

[C218] Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, and David Z. Pan, "DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node," IEEE International Conference on Computer Design (ICCD), Boston, MA, Nov. 5-8, 2017.

[C217] Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-han Kim, Praveen Raghavan, and David Z. Pan, "Patterning Aware Design Optimization of Selective Etching in N5 and Beyond," IEEE International Conference on Computer Design (ICCD), Boston, MA, Nov. 5-8, 2017.

[C216] Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, and David Z. Pan, "Optical computing on silicon-on-insulator-based photonic integrated circuits," IEEE International Conference on ASIC (ASICON), Guiyang, China, Oct. 25-28, 2017. (Invited Paper)

[C215] Yibo Lin, Xiaoqing Xu, Jiaojiao Ou and David Z Pan, "Machine learning for mask/wafer hotspot detection and mask synthesis," Photomask Technology, Oct 16, 2017. (Invited Paper)

[C214] Wei Ye, Yibo Lin, Xiaoqing Xu, Wuxi Li, Yiwei Fu, Yongsheng Sun, Canhui Zhan and David Z. Pan, "Placement Mitigation Techniques for Power Grid Electromigration," IEEE International Symposium on Low Power Electronics and Design (ISLPED), Taipei, Jul. 24-26, 2017.

[C213] Xiaoqing Xu, Yibo Lin, Vinicius Livramento, and David Z. Pan, "Concurrent Pin Access Optimization for Unidirectional Routing," ACM/IEEE Design Automation Conference (DAC), Austin, TX, Jun. 18-22, 2017.

[C212] Biying Xu, Shaolan Li, Nan Sun, and David Z. Pan, "A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology," ACM/IEEE Design Automation Conference (DAC), Austin, TX, Jun. 18-22, 2017.

[C211] Derong Liu, Vinicius Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, and David Z. Pan, "Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups," ACM/IEEE Design Automation Conference (DAC), Austin, TX, Jun. 18-22, 2017.

[C210] Meng Li, Liangzhen Lai, Vikas Chandra, and David Z. Pan, "Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack," ACM/IEEE Design Automation Conference (DAC), Austin, TX, Jun. 18-22, 2017.

[C209] Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, and Yier Jin, "AppSAT: Approximately Deobfuscating Integrated Circuits," IEEE International Symposium on Hardware Oriented Security and Trust (HOST), McLean, VA, USA, May 1-4, 2017. (Best Paper Award)

[C208] Travis Meade, Zheng Zhao, Shaojie Zhang, David Z. Pan, and Yier Jin, "Revisit Sequential Logic Obfuscation: Attacks and Defenses," IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, May 28-31, 2017 (Invited Paper)

[C207] Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin and David Z. Pan, "DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment," ACM International Symposium on Physical Design (ISPD), Portland, OR, Mar. 19-22, 2017.

[C206] Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun and David Z. Pan, "Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits," ACM International Symposium on Physical Design (ISPD), Portland, OR, Mar. 19-22, 2017.

[C205] Shounak Dhar, Mahesh Iyer, Saurabh Adya, Love Singhal, Nikolay Rubanov and David Z. Pan, "An Effective Timing-Driven Detailed Placement Algorithm for FPGAs," ACM International Symposium on Physical Design (ISPD), Portland, OR, Mar. 19-22, 2017.

[C204] Joydeep Mitra, Andres Torres, and David Z. Pan, "Process, Design Rule, and Layout Co-optimization for DSA Based Patterning of Sub-10nm Finfet Devices," SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 26 - Mar. 2, 2017

[C203] Joydeep Mitra, Andres Torres, and David Z. Pan, "Model Based Guiding Pattern Synthesis for On-target and Robust Assembly of Via and Contact layers using DSA," SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 26 - Mar. 2, 2017.

[C202] Taiki Kimura, Tetsuaki Matsunawa, Chikaaki Kodama, Shigeki Nojima and David Z. Pan, "SOCS-based post-layout optimization for multiple patterns with light interference prediction," SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 26 - Mar. 2, 2017.

[C201] Jiaojiao Ou, Brian Cline, Greg Yeric and David Z. Pan, "Efficient DSA and DP Hybrid Lithography Conflict Detection and Guiding Template Assignment," SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 26 - Mar. 2, 2017.

[C200] Travis Meade, Shaojie Zhang, Zheng Zhao, David Z. Pan, and Yier Jin, "Gate-Level Netlist Reverse Engineering Tool Set for Functionality Recovery and Malicious Logic Detection," International Symposium for Testing and Failure Analysis (ISTFA), Fort Worth, Texas, USA, Nov. 6-10, 2016.

[C199] Wuxi Li, Shounak Dhar, and David Z. Pan, "UTPlaceF: A Routability-Driven FPGA Placer with Physical and Congestion Aware Packing," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov. 7-10, 2016. (Invited Paper; 1st Place Winner of ISPD'16 Contest)

[C198] Yudong Tao, Changhao Yan, Yibo Lin, Shengguo Wang, David Z. Pan, and Xuan Zeng, "A Novel Unified Dummy Fill Insertion Framework with SQP-Based Optimization Method," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov. 7-10, 2016.

[C197] Shounak Dhar, Saurabh Adya, Love Singhal, Mahesh A. Iyer and David Z. Pan, "Detailed Placement for Modern FPGAs using 2D Dynamic Programming," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov. 7-10, 2016.

[C196] Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin and David Z. Pan, "Provably Secure Camouflaging Strategy for IC Protection," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov. 7-10, 2016.

[C195] Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert and David Z. Pan, "MrDP: Multiple-row Detailed Placement of Heterogeneous-sized Cells for Advanced Nodes," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, Nov. 7-10, 2016.

[C194] Yibo Lin, Bei Yu, and David Z. Pan, "Detailed Placement In Advanced Technology Nodes: A Survey," EEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Hangzhou, China, October 25-28, 2016. (Invited Paper)

[C193] Derong Liu, Bei Yu, Salim Chowdhury, and David Z. Pan, "Incremental Layer Assignment for Critical Path Timing," ACM/IEEE Design Automation Conference (DAC), 2016.

[C192] Meng Li, Jin Miao, Kai Zhong, and David Z. Pan, "Practical Public PUF Enabled by Solving Max-Flow Problem on Chip," ACM/IEEE Design Automation Conference (DAC), 2016.

[C191] Xiaoqing Xu, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, and David Z. Pan, "A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation," ACM International Symposium on Physical Design (ISPD), Santa Rosa, CA, April 3-6, 2016.

[C190] Jiaojiao Ou, Bei Yu, and David Z. Pan, "Concurrent Guiding Template Assignment and Redundant Via Insertion for DSA-MP Hybrid Lithography," ACM International Symposium on Physical Design (ISPD), Santa Rosa, CA, April 3-6, 2016.

[C189] Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, and David Z. Pan, "Hybrid Hotspot Detection using Regression Model and SOCS Kernels," SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 21-25, 2016.

[C188] Yibo Lin, Xiaoqing Xu, Bei Yu, Ross Baldick, and David Z. Pan, "Triple/Quadruple Patterning Layout Decomposition via Novel Linear Programming and Iterative Rounding," SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 21-25, 2016. (Best Student Paper Award)

[C187] Xiaoqing Xu, Brian Cline, Greg Yeric, and David Z. Pan, "Standard Cell Pin Access and Physical Design in Advanced Lithography," SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 21-25, 2016. (Invited Paper)

[C186] Tetsuaki Matsunawa, Bei Yu, and David Z. Pan, "Laplacian Eigenmaps and Bayesian Clustering Based Layout Pattern Sampling and Its Applications to Hotspot Detection and OPC," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Macau, Jan. 25-28, 2016.

[C185] Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert and David Z. Pan, "Stitch Aware Detailed Placement for Multiple E-Beam Lithography," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Macau, Jan. 25-28, 2016.

[C184] Pengpeng Ren, Xiaoqing Xu, Peng Hao, Junyao Wang, Runsheng Wang, Ming Li, Jianping Wang, Weihai Bu, Jingang Wu, Walsum Wong, Shaofeng Yu, Hanming Wu, Shiuh-Wuu Lee, David Z. Pan, and Ru Huang, "Adding the Missing Time-Dependent Layout Dependency into Device-Circuit-Layout Co-Optimization -- New Findings on the Layout Dependent Aging Effects," IEEE International Electron Devices Meeting (IEDM), 2015.

[C183] Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan and Gabriel Robins, "Toward Metrics of Design Automation Research Impact," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, November 2-6, 2015. (Invited Paper)

[C182] Bei Yu, Derong Liu, Salim Chowdhury and David Z. Pan, "TILA: Timing-Driven Incremental Layer Assignment," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, November 2-6, 2015.

[C181] Yibo Lin, Bei Yu, Biying Xu and David Z. Pan, "Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, November 2-6, 2015.

[C180] Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan and Deming Chen, "CSL: Coordinated and Scalable Logic Synthesis Techniques for Effective NBTI Reduction," IEEE International Conference on Computer Design (ICCD), NY, Oct 18-21, 2015.

[C179] David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin, "Pushing Multiple Patterning in Sub-10nm: Are We Ready?," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015. (Invited Paper)

[C178] Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, and David Z. Pan, "PARR: Pin Access Planning and Regular Routing for Self-Aligned Double Patterning," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015.

[C177] Yibo Lin, Bei Yu, and David Z. Pan, "High Performance Dummy Fill Insertion with Coupling and Uniformity Constraints," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015.

[C176] Subhendu Roy, Derong Liu, Junhyung Um, and David Z. Pan, "OSFA: A New Paradigm of Gate Sizing for Power/Performance Optimizations under Multiple Operating Conditions," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015.

[C175] Keith Campbell, Pranay Vissa, David Z. Pan, and Deming Chen, "High-Level Synthesis of Error Detecting Cores through Low-Cost Modulo-3 Shadow Datapaths," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015.

[C174] Wei Ye, Bei Yu, Yong-Chan Ban, Lars Liebmann, and David Z. Pan, "Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line," ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, PA, May 20-22, 2015.

[C173] Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, Moshe Preil, Azat Latypov, and David Z Pan, "Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design," ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, PA, May 20-22, 2015.

[C172] Subhendu Roy, Pavlos M Mattheakis, Peter S Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet and David Z Pan, "Skew Bounded Buffer Tree Resynthesis for Clock Power Optimization," ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, PA, May 20-22, 2015.

[C171] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, and David Z. Pan, "A Systematic Framework for Evaluating Standard Cell Middle-of-Line (MOL) Robustness for Multiple Patterning," SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability IX, San Jose, CA, Feb. 23-27, 2015.

[C170] Tetsuaki Matsunawa, Jhih-Rong Gao, Bei Yu, and David Z. Pan, "A New Lithography Hotspot Detection Framework Based on AdaBoost Classifier and Simplified Feature Extraction," SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability IX, San Jose, CA, Feb. 23-27, 2015.

[C169] Tetsuaki Matsunawa, Bei Yu, and David Z. Pan, "Optical proximity correction with hierarchical Bayes model," SPIE Intl. Symp. Advanced Lithography - Optical Microlithography XXVIII, San Jose, CA, Feb. 23-27, 2015.

[C168] Bei Yu, David Z. Pan, Tetsuaki Matsunawa, and Xuan Zeng, "Machine Learning and Pattern Matching in Physical Design," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 19-22, 2015. (Invited Paper)

[C167] Jiwoo Pak, Bei Yu, and David Z. Pan, "Electromigration-aware Redundant Via Insertion," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 19-22, 2015.

[C166] Subhendu Roy, Mihir Choudhury, Ruchir Puri, and David Z. Pan, "Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 19-22, 2015.

[C165] Subhendu Roy, Pavlos Matthaiakis, Pavlos, Laurent Masse-Navette, and David Z. Pan, "Evolving Challenges and Techniques for Nanometer SoC Clock Network Synthesis," IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, China, October 28-31, 2014. (Invited Paper)

[C164] Bei Yu, Gilda Garreton, and David Z. Pan, "Layout Compliance for Triple Patterning Lithography: an Iterative Approach," SPIE/BACUS Photomask Symposium, Monterey, CA, September 2014. (Invited Paper)

[C163] Jhih-Rong Gao, Xiaoqing Xu, Bei Yu, and David Z. Pan, "MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 1-5, 2014.

[C162] Bei Yu and David Z. Pan, "Layout Decomposition for Quadruple Patterning Lithography and Beyond," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 1-5, 2014.

[C161] Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Through-Silicon-Via Material Property Variation Impact on Full-Chip Reliability and Timing," IEEE International Interconnect Technology Conference (IITC), San Jose, CA, May 20-23, 2014.

[C160] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu and David Z. Pan, "Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization," ACM International Symposium on Physical Design (ISPD), Petaluma, CA, March 2014.

[C159] Yilin Zhang and David Z. Pan, "Timing-Driven, Over-the-Block Rectilinear Steiner Tree Construction with Pre-Buffering and Slew Constraints," ACM International Symposium on Physical Design (ISPD), Petaluma, CA, March 2014.

[C158] Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, and David. Z. Pan, "Clock Tree Resynthesis for Multi-corner Multi-mode Timing Closure," ACM International Symposium on Physical Design (ISPD), Petaluma, CA, March 2014. (Best Paper Award)

[C157] Bei Yu, Jhih-Rong Gao, Xiaoqing Xu, and David Z. Pan, "Bridging the Gap from Mask to Physical Design for Multiple Patterning Lithography," SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability VIII, San Jose, CA, Feb. 23-27, 2014. (Invited Paper)

[C156] Jhih-Rong Gao, Bei Yu, and David Z. Pan, "Accurate Lithography Hotspot Detection Based on PCA-SVM Classifier with Hierarchical Data Clustering," SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability VIII, San Jose, CA, Feb. 23-27, 2014.

[C155] Jhih-Rong Gao, Bei Yu, David Z. Pan, "Self-aligned Double Patterning Layout Decomposition with Complementary E-Beam Lithography," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Singapore, Jan. 20-23, 2014

[C154] Yilin Zhang, Salim Chowdhury, David Z. Pan, "BOB-Router: A New Buffering-Aware Global Router with Over-the-Block Routing Resources Optimization," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Singapore, Jan. 20-23, 2014

[C153] Subhendu Roy and David Z. Pan, "Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown," IEEE/ACM International Conference on VLSI Design (VLSID), Mumbai, India, Jan. 5-9, 2014

[C152] Jiwoo Pak, Sung Kyu Lim and David Z. Pan, "Electromigration Study for Multi-scale Power/Ground Vias in TSV-based 3D ICs," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 18-21, 2013.

[C151] Bei Yu, Xiaoqing Xu, Jhih-Rong Gao and David Z. Pan, "Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 18-21, 2013. (William J. McCalla Best Paper Award)

[C150] Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas and David Z. Pan, "A High-Performance Triple Patterning Layout Decomposer with Balanced Density," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 18-21, 2013.

[C149] Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert and David Z. Pan, "Clock Power Minimization using Structured Latch Templates and Decision Tree Induction," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 18-21, 2013.

[C148] Jhih-Rong Gao, Bei Yu, Duo Ding, and David Z. Pan, "Lithography Hotspot Detection and Mitigation in Nanometer VLSI," IEEE International Conference on ASIC (ASICON) , Shenzhen, China, Oct. 28-31, 2013. (Invited Paper)

[C147] Subhendu Roy, Mihir Choudhury, Ruchir Puri, and David Z. Pan, "Towards Optimal Performance-Area Trade-off in Adders by Synthesis of Parallel Prefix Structures," ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2-6, 2013.

[C146] Yang Li and David Z. Pan, "An Accurate Semi-Analytical Framework for Full-Chip TSV-induced Stress Modeling," ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2-6, 2013.

[C145] Bei Yu, Kun Yuan, Jhih-Rong Gao, and David Z. Pan, "E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System," ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2-6, 2013.

[C144] Bei Yu, Jhih-Rong Gao, and David Z. Pan, "Triple-patterning Lithography (TPL) Layout Decomposition using End Cutting," SPIE Intl. Symp. Advanced Lithography, San Jose, CA, Feb. 24-28, 2013.

[C143] Jhih-Rong Gao, Harshdeep Jawandha, Prasad Atkarc, Atul Walimbe, Bikram Baidya, and David Z. Pan, "Self-aligned Double Patterning Compliant Routing with In-design Physical Verification Flow," SPIE Intl. Symp. Advanced Lithography, San Jose, CA, Feb. 24-28, 2013.

[C142] Jhih-Rong Gao, Bei Yu, Ru Huang, and David Z. Pan, "Self-aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement," SPIE Intl. Symp. Advanced Lithography, San Jose, CA, Feb. 24-28, 2013.

[C141] Bei Yu, Jhih-Rong Gao, and David Z. Pan, "L-Shape based Layout Fracturing for E-Beam Lithography," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, January 22- 25, 2013. (Best Paper Award Nomination)

[C140] Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-seok Yang, Kun Yuan, Minsik Cho, and David Z. Pan, "Dealing with IC Manufacturability in Extreme Scaling," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 5-8, 2012. (Embedded Tutorial Paper)

[C139] Jiwoo Pak, Sung Kyu Lim, and David Z. Pan, "Electromigration-aware Routing for 3D ICs with Stress-aware EM Modeling," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-8, 2012.

[C138] Yen-Hung Lin, Bei Yu, David Z. Pan and Yih-Lang Li, "TRIAD: A Triple Patterning Lithography Aware Detailed Router," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-8, 2012.

[C137] Yilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, and David Z. Pan, "Reclaiming Over-the-IP-Block Routing Resources With Buffering-Aware Rectilinear Steiner Minimum Tree Construction," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-8, 2012.

[C136] Jiwoo Pak, Mohit Pathak, Sung Kyu Lim, and David Z. Pan, "Modeling and Prediction of Chip-level Electromigration for TSV-based 3D ICs", SRC Techcon Conference, Austin, TX, Sept. 10-11, 2012. (Best in Session Award)

[C135] Samuel I. Ward, Duo Ding, and David Z. Pan, "PADE: A High-Performance Mixed-Size Placer with Automatic Datapath Extraction and Evaluation through High-Dimensional Data Learning," ACM/IEEE Design Automation Conference (DAC) , 2012.

[C134] Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Chip/Package Co-Analysis of Thermo-Mechanical Stress and Reliability in TSV-based 3D ICs," ACM/IEEE Design Automation Conference (DAC) , 2012. (Nominated for Best Paper Award)

[C133] David Z. Pan, Jhih-Rong Gao and Bei Yu, "VLSI CAD for Emerging Nanolithography," International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2012. (Invited Paper)

[C132] Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles Alpert, Earl Swartzlander, and David Z. Pan, "Keep it Straight: Teaching Placement how to Better Handle Designs with Datapaths," ACM International Symposium on Physical Design (ISPD), Napa Valley, CA, March, 2012. (Nominated for Best Paper Award)

[C131] Jhih-Rong Gao an David Z. Pan, "Flexible Self-aligned Double Patterning Aware Detailed Routing with Prescribed Layout Planning," ACM International Symposium on Physical Design (ISPD), Napa Valley, CA, March, 2012

[C130] Kevin Lucas, Chris Cork, Gerry Luk-Pat, Ben Painter, Bei Yu, and David Z. Pan, "Implications of triple patterning for 14 nm node design and patterning," SPIE Advanced Lithography Symposium Design for Manufacturability through Design-Process Integration VI (Conference 8327), Feb. 2012. (Keynote Presentation and Invited Paper)

[C129] Vijay J. Reddi, David Z. Pan, Sani R. Nassif, and Keith A. Bowman, "Robust and Resilient Designs from the Bottom-Up: Technology, Circuit, CAD and System Issues," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Sydney, Australia, Jan. 30-Feb. 3, 2012. (Invited Special Session Paper)

[C128] David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, and Jae-seok Yang, "Design for Manufacturability and Reliability for TSV-based 3D ICs," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Sydney, Australia, Jan. 30-Feb. 3, 2012. (Invited Special Session Paper)

[C127] Duo Ding, Bei Yu, Joydeep Ghosh, and David Z. Pan, "EPIC: Efficient Prediction of IC Manufacturing Hotspots With A Unified Meta-Classification Formulation," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Sydney, Australia, Jan. 30-Feb. 3, 2012. (Best Paper Award)

[C126] Duo Ding, Bei Yu, and David Z. Pan, "GLOW: A Global Router for Low-Power Thermal-reliable Interconnect Synthesis using Photonic Wavelength Multiplexing," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Sydney, Australia, Jan. 30-Feb. 3, 2012

[C125] Duo Ding and David Z. Pan, "Low-power Integration of On-chip Nanophotonic Interconnect for High-performance Opto-electrical IC," Proc. SPIE Optoelectronic Integrated Circuits XIV, Jan. 25-26, 2012 (Invited Paper)

[C124] Ryan A. Integlia, Lianghong Yin, Duo Ding, David Z. Pan, Douglas M. Gill, and Wei Jiang, "Parallel-coupled dual racetrack silicon micro-resonators for quadrature amplitude modulation" Proc. SPIE Silicon Photonics VII , Jan. 22-25, 2012

[C123] Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding and David Z. Pan, "Layout Decomposition for Triple Patterning Lithography," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011 (Finalist for William J. McCalla Best Paper Award)

[C122] Yen-Hung Lin, Yong-Chan Ban, David Z. Pan and Yih-Lang Li, "DOPPLER: DPL-aware and OPC-friendly Gridless Detailed Routing with Mask Density Balancing," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011

[C121] Moongon Jung, Xi Liu, Suresh Sitaraman, David Z. Pan and Sung Kyu Lim, "Full-Chip Through-Silicon-Via Interfacial Crack Analysis and Optimization for 3D IC," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011

[C120] Mohit Pathak, Jiwoo Pak, David Z. Pan and Sung Kyu Lim, "Electromigration Modeling and Full-chip Reliability Analysis for BEOL Interconnect in TSV-based 3D ICs," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011

[C119] Wooyoung Jang, Ou He, Jae-Seok Yang and David Z. Pan, "Chemical-Mechanical Polishing Aware Application-Specific 3D NoC Design," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011

[C118] Moongon Jung, Joydeep Mitra, David Z. Pan, and Sung Kyu Lim, "TSV Stress-aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC," ACM/IEEE Design Automation Conference (DAC), San Diego, June 2011. (Nominated for Best Paper Award)

[C117] Yongchan Ban, Kevin Lucas, and David Z. Pan, "Flexible 2D Layout Decomposition Framework for Spacer-type Double Pattering Lithography," ACM/IEEE Design Automation Conference (DAC), San Diego, June 2011.

[C116] Duo Ding, Jhih-Rong Gao, Kun Yuan and David Z. Pan "AENEID: A Generic Lithography-friendly Detailed Router based on Post RET Data Learning and Hotspot Detection," ACM/IEEE Design Automation Conference (DAC), San Diego, June 2011.

[C115] Yongchan Ban and Jae-Seok Yang, "Layout Aware Line-Edge Roughness Modeling and Poly Optimization for Leakage Minimization," ACM/IEEE Design Automation Conference (DAC), San Diego, June 2011.

[C114] Joydeep Mitra, Moongon Jung, Rui Huang, Suk-Kyu Ryu, Sung Kyu Lim, and David Z. Pan, "A Fast Simulation Framework for Full-Chip Thermo-Mechanical Stress and Reliability Analysis of Through-Silicon-Via based 3D ICs," IEEE Electronic Components and Technology Conference (ECTC), May 2011.

[C113] Jiwoo Pak, Mohit Pathak, Sung Kyu Lim and David Z. Pan, "Modeling of Electromigration in Through-Silicon-Via Based 3D IC," IEEE Electronic Components and Technology Conference (ECTC), May 2011.

[C112] Kun Yuan and David Z. Pan, "E-Beam Lithography Stencil Planning and Optimization with Overlapped Characters," ACM International Symposium on Physical Design (ISPD), March 2011 (Best Paper Award)

[C111] Yongchan Ban, Soo-Han Choi, Kevin Lucas, Chul-Hong Park and David Z. Pan, "Layout Decomposition of Self-Aligned Double Patterning for 2D Random Logic Patterning," SPIE Intl. Symp. Advanced Lithography, February 27 - March 3, 2011

[C110] Chul-Hong Park, David Z. Pan, and Kevin Lucas, "Exploration of VLSI CAD Researches for Early Design Rule Evaluation," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 2011 (Invited Paper)

[C109] Duo Ding, Andres J. Torres, Fedor G. Pikus and David Z. Pan, "High Performance Lithographic Hotspot Detection using Hierarchically Refined Machine Learning," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 2011

[C108] Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim and David Z. Pan, "Robust Clock Tree Synthesis with Timing Yield Optimization for 3DICs," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 2011

[C107] Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, and Giovanni De Micheli, "CELONCEL: Effective Design Technique for 3D Monolithic Integration targeting High Performance Integrated Circuits," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 2011

[C106] Ashutosh Chakraborty and David Z.Pan, "Controlling NBTI Degradation during Static Burn-in Testing," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Japan, Jan. 2011

[C105] Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan and Sung Kyu Lim, "Stress-Driven 3D-IC Placement with TSV Keep-Out Zone and Regularity Study," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2010, San Jose, CA, November 2010

[C104] Minsik Cho, David Z. Pan and Ruchir Puri, "Novel Binary Linear Programming for High Performance Clock Mesh Synthesis," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2010, San Jose, CA, November 2010

[C103] Kun Yuan and David Z. Pan, "WISDOM: Wire Spreading Enhanced Decomposition of Masks in Double Patterning Lithography", IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2010, San Jose, CA, November 2010.

[C102] Ashutosh Chakraborty and David Z. Pan, "PASAP: Power Aware Structured ASIC Placement," IEEE International Symposium on Low Power Electronics Design (ISLPED), Austin, TX, August 2010. Slides

[C101] David Z. Pan, Jae-Seok Yang, Kun Yuan, and Minsik Cho, "CAD for Double Patterning Lithography", IEEE International Conference on IC Design and Technology (ICICDT), Grenoble, France, June 2010 (Invited Paper)

[C100] Wooyoung Jang, Duo Ding and David Z. Pan, "Voltage and Frequency Island Optimizations for Many-core/NoC Designs," The First International Conference on Green Circuits and Systems (ICGCS) , Shanghai, China, June 2010 (Invited Paper)

[C99] Wooyoung Jang and David Z. Pan, "Application-Aware NoC Design for Efficient SDRAM Access," ACM/IEEE Design Automation Conference (DAC), California, June 2010

[C98] Yongchan Ban and David Z. Pan, "Compact Modeling and Robust Layout Optimization for Contacts in Deep Subwavelength Lithography," ACM/IEEE Design Automation Conference (DAC), California, June 2010.

[C97] Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, and David Z. Pan, "TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization," ACM/IEEE Design Automation Conference (DAC), California, June 2010.

[C96] Anurag Kumar, Minsik Cho, and David Z. Pan, "DNA Microarray Placement for Improved Performance and Reliability," International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2010.

[C95] Yongchan Ban, S. Sundareswaran, and David Z. Pan, "Total Sensitivity Based DFM Optimization of Standard Library Cells," ACM International Symposium on Physical Design (ISPD), San Francisco, California, March 2010.

[C94] Ashutosh Chakraborty and David Z. Pan, "Skew Management of NBTI Impacted Gated Clock Trees," ACM International Symposium on Physical Design (ISPD), San Francisco, California, March 2010. (Nominated for Best Paper Award) Slides

[C93] Yongchan Ban, Yuansheng Ma, Harry J. Levinson, Yunfei Deng, Jongwook Kye, and David Z. Pan, "Modeling and characterization of contact edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell," SPIE Intl.Symp. Advanced Lithography, February 2010

[C92] Wooyoung Jang, David Z. Pan, "A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Taiwan, Jan. 2010.

[C91] Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, and David Z. Pan, "A New Graph Theoretic, MultiObjective Layout Decomposition Framework for Double Patterning Lithography," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Taiwan, Jan. 2010. (Best Paper Award)
(IBM Research Pat Goldberg Memorial Best Paper Award for 2010 in Computer Science, Electrical Engineering and Math)

[C90] David Z. Pan, Jae-seok Yang, Kun Yuan, Minsik Cho, and Yongchan Ban, "Layout Optimizations for Double Patterning Lithography," IEEE 8th International Conference on ASIC (ASICON), Changsha, China, Oct. 2009. (Invited Paper)

[C89] Yongchan Ban, Savithri Sundareswaran, and David Z. Pan, "Comprehensive Standard Cell Characterization Considering Random Line-Edge Roughness Lithography Variation," , SRC Techcon Conference, Austin, TX, September 2009.

[C88] Katrina Lu and David Z. Pan, "Reliability-aware Global Routing under Thermal Considerations," Asia Symposium on Quality Electronic Design (ASQED), Malaysia, July 2009.

[C87] Duo Ding and David Z. Pan, "OIL: A Nanophotonic Optical Interconnect Library for a New Photonic Networks-on-Chip Architecture," International Workshop on System Level Interconnect Prediction (SLIP), California, July 2009.

[C86] Kun Yuan, Katrina Lu, and David Z. Pan, "Double Patterning Lithography Friendly Detailed Routing with Redundant Via Consideration," ACM/IEEE Design Automation Conference (DAC), California, July 2009.

[C85] Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, and David Z. Pan, "O-Router: An Optical Routing Framework for Low Power On-Chip Silicon Nano-Photonic Integration," ACM/IEEE Design Automation Conference (DAC), California, July 2009.

[C84] Ashutosh Chakraborty, Anurag Kumar, and David Z. Pan, "RegPlace: A High Quality Opensource Placement Framework for Structured ASICs," ACM/IEEE Design Automation Conference (DAC), California, July 2009. (Grand Prize $25,000 Winner of the eASIC Placement Worldwide Contest)

[C83] Wooyoung Jang and David Z. Pan, "An SDRAM-Aware Router for Networks-on-Chip," ACM/IEEE Design Automation Conference (DAC), California, July 2009.

[C82] Duo Ding, Xiang Wu, Joydeep Ghosh, and David Z. Pan, "Machine Learning based Lithographic Hotspot Detection with Critical Feature Extraction and Classification," IEEE International Conference on IC Design and Technology (ICICDT), Austin, TX, May 2009. (Best Student Paper Award)

[C81] Yong-Chan Ban, David Z. Pan, Savithri Sundareswaran and Rajendran Panda, "Electrical Impact of Line-Edge Roughness on Sub-45nm Node Standard Cell," Intl.Symp. SPIE Advanced Lithography, February 2009.

[C80] Kun Yuan, Jae-Seok Yang and David Z. Pan, "Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization," ACM International Symposium on Physical Design (ISPD), San Diego, March 2009.

[C79] Ashutosh Chakraborty and David Z. Pan, "On Stress Aware Active Area Sizing, Gate Sizing, and Repeater Insertion," ACM International Symposium on Physical Design (ISPD), San Diego, March 2009.

[C78] Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram and David Z. Pan, "Analysis and Optimization of NBTI Induced Clock Skew in Gated Clock Trees," IEEE/ACM Design, Automation & Test in Europe (DATE), Nice, France, April 2009. (Best Paper/IP Award)

[C77] Peng Yu, Xi Chen, David Z. Pan, and Andrew Ellington, "Synthetic Biology Design and Analysis: a Case Study of Frequency Entrained Biological Clock," IEEE International Conference on Bioinformatics and Biomedicine (BIBM'08), November 2008.

[C76] David Z. Pan, Minsik Cho, Kun Yuan, and Yongchan Ban, "Lithography Friendly Routing: From Construct-by-Correction to Correct-by-Construction," IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Beijing, October 2008. (Invited Paper)

[C75] Shanhu Shen, Peng Yu, and David Z. Pan, "Enhanced DCT2-based Inverse Mask Synthesis with Initial SRAF Insertion", SPIE/BACUS Photomask Symposium, October 2008.

[C74] Jae-Seok Yang and David Z. Pan, "Overlay Aware Interconnect and Timing Variation Modeling for Double Patterning Technology," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2008

[C73] Wooyoung Jang, Duo Ding and David Z. Pan, "A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2008.

[C72] Tao Luo, David A. Papa, Zhuo Li, C. N. Sze, Charles J. Alpert and David Z. Pan, "Pyramids: An Efficient Computational Geometry-based Approach for Timing-driven Placement," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2008. (Nominated for Best Paper Award)

[C71] Minsik Cho, Yongchan Ban and David Z. Pan, "Double Patterning Technology Friendly Detailed Routing," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2008.

[C70] Anand Rajaram and David Z. Pan, "Robust Chip-Level Clock Tree Synthesis for SOC Designs," ACM/IEEE Design Automation Conference (DAC), California, June 2008.

[C69] Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan, "An Integrated Nonlinear Placement Framework with Congestion and Porosity Aware Buffer Planning," ACM/IEEE Design Automation Conference (DAC), California, June 2008.

[C68] Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan, "ELIAD: Efficient Lithography Aware Detailed Router with Compact Printability Prediction," ACM/IEEE Design Automation Conference (DAC), California, June 2008.

[C67] Tung-Chieh Chen, Minsik Cho, David Z. Pan and Yao-Wen Chang, "Metal-Density Driven Placement for CMP Variation and Routability," ACM International Symposium on Physical Design (ISPD), Portland, April 2008.

[C66] Minsik Cho and D. Z. Pan, "A High-Performance Droplet Router for Digital Microfluidic Biochips," ACM International Symposium on Physical Design (ISPD), Portland, April 2008.

[C65] S. X. Shi, A. Ramalingam, D. Wang, and D. Z. Pan, "Latch Modeling for Statistical Timing Analysis," IEEE/ACM Design, Automation & Test in Europe (DATE), Munich, Germany, March 2008.

[C64] Ashutosh Chakraborty, S. X Shi, David Z. Pan, "Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices," IEEE/ACM Design, Automation & Test in Europe (DATE), Munich, Germany, March 2008.

[C63] David Z. Pan and Minsik Cho, "Synergistic Physical Synthesis for Manufacturability/Variability in 45nm Designs and Beyond," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008. (Invited Paper)

[C62] Tao Luo, David Z. Pan, "DPlace 2.0: A Stable and Efficient Analytical Placement based on Diffusion," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008.

[C61] Tao Luo, David Newmark, David Z. Pan, "Total Power Optimization Combining Placement, Sizing and Multi-Vt Through Slack Distribution Management," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008.

[C60] Anand Rajaram and David Z. Pan, "MeshWorks: An Efficient Framework for Planning, Synthesis and Optimization of Clock Mesh Networks," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008. (Nominated for Best Paper Award)

[C59] Peng Yu and David Z. Pan, "TIP-OPC: A New Topological Invariant Paradigm for Pixel Based Optical Proximity Correction," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2007.

[C58] Peng Yu and David Z. Pan, "A Novel Intensity Based OPC Algorithm with Speedup in Lithography Simulation," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2007.

[C57] Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan, "BoxRouter 2.0: Architecture and Implementation of a Hybrid and Robust Global Router," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2007.

[C56] Peng Yu and David Z. Pan, "TIP-OPC: A New Topological Invariant Paradigm for Pixel Based Optical Proximity Correction", SRC Techcon Conference, September, 2007.

[C55] Tao Luo, David Newmark, David Z. Pan, "Effective Power Optimization combining Placement, Sizing and Multi-Vt techniques", SRC Techcon Conference, September, 2007 (Best Paper in Session)

[C54] Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky and David Z. Pan, "Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis," ACM/IEEE Design Automation Conference (DAC), June, 2007.

[C53] Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "TROY: Track Router with Yield-driven Wire Planning," ACM/IEEE Design Automation Conference (DAC), June 2007.

[C52] Joon-Sung Yang, Anand Rajaram, Ningyu Shi, Jian Chen and David Z. Pan, "Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis," International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2007.

[C51] A. Ramalingam, G.V. Devarayanadurg, and D. Z. Pan, "Accurate Power Grid Analysis with behavioral Transistor Network Modeling," International Symposium on Physical Design (ISPD), Austin, March 2007.

[C50] P. Yu and D. Z. Pan, "Fast Predictive Post-OPC Contact/Via Printability Metric and Validation," Proc. of SPIE Optical Microlithography XX,  Vol. 6520, 2007.

[C49] Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky and David Z. Pan, "Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis," ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Austin, Texas, Feb  2007.

[C48] H. Ren, D. Z. Pan, C. Alpert, G.-J. Nam, and P. Villarrubia, "Hippocrates: First-Do-No-Harm Detailed Placement'', IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2007.

[C47] M. Cho, H. Xiang, R. Puri, and D. Z. Pan, "Wire Density Driven Global Routing for CMP Variation and Timing," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2006.

[C46] S. X Shi, P. Yu, and D. Z. Pan, "A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2006.

[C45] A. Ramalingam, A. K. Singh, S. R. Nassif, G.-J. Nam, M. Orshansky, and D. Z. Pan, "An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2006.

[C44] A. Dutta and D. Z. Pan, "Partial Functional Manipulation Based Wirelength Minimization," IEEE International Conference on Computer Design (ICCD), Oct. 2006.

[C43] P. Yu, S. X. Shi and D. Z. Pan, "Process Variation Aware OPC with Variational Lithography Modeling," ACM/IEEE Design Automation Conference (DAC), San Francisco, California, July, 2006.

[C42] M. Cho and D. Z. Pan, "BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP," ACM/IEEE Design Automation Conference (DAC), San Francisco, California, July, 2006. (Nominated for Best Paper Award, 12 out of 865 submissions)

[C41] T. Luo, D. Newmark and D. Z. Pan, "A New LP Based Incremental Timing Driven Placement for High Performance Designs," ACM/IEEE Design Automation Conference (DAC), San Francisco, California, July, 2006.

[C40] M. Cho and D. Z. Pan, "PEAKASO: Peak-Temperature Aware Scan-Vector Optimization," VLSI Test Symposium, Berkeley, CA (VTS), May 2006.

[C39] A. Rajaram and D. Z. Pan, Variation Tolerant Buffered Clock Network Synthesis with Cross Links," ACM International Symposium on Physical Design (ISPD), San Francisco, CA, April 2006. (covered by EE Times on April 17, 2006 in the report "Paths to better timing analysis,"by Richard Goering)

[C38] A. Havlir and D. Z. Pan, "Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines," IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2006.

[C37] A. Ramalingam, F. Liu, S. R. Nassif, and D. Z. Pan, "Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity," IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2006.

[C36] A. Rajaram and D. Z. Pan, "Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction," IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2006.

[C35] P. Yu, D. Z. Pan and C. A. Mack, Fast Lithography Simulation under Focus Variations for OPC and Layout Optimizations," SPIE Design and Process Integration for Microelectronic Manufacturing IV, Feb. 2006.

[C34] M. Cho, H. Shin and D. Z. Pan, "Fast Substrate Noise-Aware Floorplanning with Preference Directed Graph for Mixed-Signal SOCs," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2006, (Nominated for Best Paper Award, 8 out of 424 submissions).

[C33] S. X. Shi and D. Z. Pan, "Wire Sizing and Shaping with Scattering Effect for Nanoscale Interconnection," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2006.

[C32] A. Ramalingam, S. V. Kodakara, A. Devgan and D. Z. Pan, "Robust Analytical Gate Delay Modeling for Low Voltage Circuits," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Yokohama City, Japan, Jan. 2006.

[C31] T. Luo, H. Ren, C. Alpert and D. Z. Pan, "Computational Geometry Based Placement Migration," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2005.

[C30] M. Cho, S. Ahmed and D. Z. Pan, "TACO: Temperature Aware Clock Optimization," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2005. (covered by EE Times on June 19, 2006 in the report "Chip designers feel the heat,"by Richard Goering)

[C29] D. Z. Pan, "Lithography Aware Physical Design," IEEE 6th International Conf. on ASIC (ASICON), Shanghai, Oct. 24-27, 2005. (Invited Paper at the Special Session on DFM)

[C28] J. Mitra, P. Yu and D. Z. Pan, "RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations," ACM/IEEE Design Automation Conference (DAC), Anaheim, California, June, 2005.

[C27] H. Ren, D. Z. Pan, C. Alpert and P. Villarrubia, "Diffusion Based Placement Migration," ACM/IEEE Design Automation Conference (DAC), Anaheim, California, June, 2005.

[C26] D. Z. Pan and M. D. F. Wong, "Manufacturability Aware Physical Layout Optimizations," IEEE International Conference on IC Design and Technology (ICICDT), Austin, TX, May 2005. (Invited Paper)

[C25] J. Mitra and P. Yu and D. Z. Pan,"RADAR: RET-Aware Detailed Routing", Electronic Design Process (EDP) Workshop, Monterey, California, April, 2005.

[C24] H. Ren, D. Z. Pan, C. Alpert and P. Villarrubia, "Diffusion Based Placement Migration", Electronic Design Process (EDP) Workshop,  Monterey, California, April, 2005.

[C23] A. Rajaram, D. Z. Pan and J. Hu, "Improved Algorithms for Link Based Non-tree Clock Network for Skew Variability Reduction," ACM International Symposium on Physical Design (ISPD), San Francisco, CA, April 2005.

[C22] A. Ramalingam, B. Zhang, A. Devgan, and D. Z. Pan, "Sleep Transistor Sizing Using Timing Criticality and Temporal Currents," IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2005.

[C21] G. Xu, L. Huang, D. Z. Pan and M. D.-F. Wong, "Redundant-Via Enhanced Maze Routing for Yield Improvement," IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC),  Jan. 2005.

[C20] G. Xu, R. Tian, D. Z. Pan and M. D.-F. Wong, "CMP Aware Shuttle Mask Floorplanning," IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2005.

[C19] H. Ren, D. Z. Pan and P. Villarrubia, "True Crosstalk Aware Incremental Placement with Noise Map," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2004.

[C18] G. Xu, R. Tian, D. Z. Pan and M. D.F. Wong, "A Multi-objective Floorplanner for Shuttle Mask Optimization," SPIE International Symp. on Photomask Technology, Sept. 2004.

[C17] H. Ren, D. Z. Pan and D. S. Kung, "Sensitivity Guided Netweighting for Placement Driven Synthesis," ACM International Symposium on Physical Design (ISPD), Phoenix, Arizona, April 2004.

[C16] R. Puri, L. Stok, J. Cohn, D. Kung, D. Z. Pan, D. Sylvester, A. Srivastava, and S. H. Kulkarni, "Pushing ASIC Performance in a Power Envelope," ACM/IEEE Design Automation Conference (DAC), Anaheim, California, June, 2003.

[C15] D. Z. Pan, A. Correale, D. Lamb, D. Wallach, D. Kung, and R. Puri, "Generic Voltage Island: CAD Flow and Design Experience", Austin Conference on Energy Efficient Design (ACEED), Austin, Texas, Feb, 2003.

[C14] R. Puri, D. Z. Pan and D. Kung, "A Flexible Design Approach for the Use of Dual Supply Voltages and Level Conversion for Low-Power ASIC Design", Austin Conference on Energy Efficient Design (ACEED), Austin, Texas, Feb, 2003.

[C13] C.-C. Chang, J. Cong, D. Z. Pan and X. Yuan, "Physical Hierarchy Generation with Routing Congestion and Control," ACM International Symposium on Physical Design (ISPD), pp36-41, San Diego, California, April 2002.

[C12] J. Cong, D. Z. Pan and P.V. Srinivas, "Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization," IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), Jan. 30 - Feb. 2, 2001, Pacifico Yokohama, Japan.

[C11] J. Cong, D. Z. Pan and P.V. Srinivas, "Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization," ACM TAU Workshop, Dec. 4-5, 2000, Austin.

[C10] C.-C. Chang, J. Cong, D. Z. Pan and X. Yuan, " Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization," SRC Techcon Conference, September 21-3, 2000, Phoenix.

[C9] J. Cong, D. Z. Pan and P.V. Srinivas, " Improved Crosstalk Modeling with Applications to Noise Constrained Interconnect Optimization," SRC Techcon Conference, September 21-3, 2000, Phoenix.

[C8] J. Cong, T. Kong and D. Z. Pan, "Buffer Block Planning for Interconnect-Driven Floorplanning," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , November, 1999.

[C7] J. Cong and D. Z. Pan, "Interconnect Estimation and Planning for Deep Submicron Designs," ACM/IEEE 36th Design Automation Conference (DAC) , June 20-5, 1999, New Orleans.

[C6] J. Cong and D. Z. Pan, "Interconnect Delay and Area Estimation for Multiple-Pin Nets," ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 8-9, 1999, Monterey. 

[C5] J. Cong and D. Z. Pan, "Interconnect Delay Estimation Models for Synthesis and Design Planning," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), January 18-21, 1999, Hong Kong.

[C4] J. Cong and D. Z. Pan, "Interconnect Delay Estimation Models for Logic and High Level Synthesis," SRC Techcon Conference, September 9-11, 1998, Las Vegas. (Best Paper in Session Award)

[C3] J. Cong and D. Z. Pan, " Interconnect Performance Estimation Models for Synthesis and Design Planning," ACM/IEEE International Workshop on Logic Synthesis, June, 1998.

[C2] J. Cong, L. He, C.-K. Koh and Z. Pan,  "Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 1997.

[C1] J. Cong, L. He, K.-Y. Khoo, C.-K. Koh and Z. Pan, "Interconnect Design for Deep Submicron ICs," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 1997. (Embedded Tutorial)


JOURNAL ARTICLES PAPERS (Go to Top)

[J145] Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Daniel de Araujo, Jay Reddy, Adam Klivans, and David Z. Pan, “ISOP+: Machine Learning- Assisted Inverse Stack-Up Optimization for Advanced Package Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Aug. 2023 (accepted)

[J144] Arman Roohi, Sepehr Tabrizchi, Mehrdad Morsali, David Z. Pan, and Shaahin Angizi, “PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Aug. 2023 (accepted)

[J143] Shaahin Angezi, Sepehr Tabrizchi, David Z. Pan, and Arman Roohi, “PISA: A Non-Volatile Processing-In-Sensor Accelerator for Imaging Systems,” IEEE Transactions on Emerging Topics in Computing (TETC), July 2023 (accepted)

[J142] Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, and Nan Sun, “A Bandwidth-Adaptive Pipelined SAR ADC with Three-Stage Cascoded Floating Inverter Amplifier,” IEEE Journal of Solid-State Circuits (JSSC), April 2023 (accepted)

[J141] Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, and Nan Sun, “An In-Memory-Computing Charge-Domain Ternary CNN Classifier,” IEEE Journal of Solid-State Circuits (JSSC), Jan. 2023 (accepted)

[J140] Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, and David Z. Pan, "1MS/s and 80MS/s SAR ADCs in 40nm CMOS with End-to-End Compilation," IEEE Solid-State Circuits Letters, 2022. (accepted)

[J139] Chenghao Feng*, Jiaqi Gu*, Hanqing Zhu, Zhoufeng Ying, Zheng Zhao, David Z. Pan and Ray T. Chen, "A compact butterfly-style silicon photonic-electronic neural chip for hardware-efficient deep learning," ACS Photonics, Nov., 2022.

[J138] Xiaohan Gao, Haoyi Zhang, Mingjie Liu, Linxiao Shen, David Z. Pan, Yibo Lin, Runsheng Wang, Ru Huang, "Interactive Analog Layout Editing with Instant Placement and Routing Legalization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Jul., 2022.

[J137] Jiaqi Gu, Chenghao Feng, Hanqing Zhu, Zheng Zhao, Zhoufeng Ying, Mingjie Liu, Ray T. Chen and David Z. Pan, "SqueezeLight: A Multi-Operand Ring-Based Optical Neural Network with Cross-Layer Scalability," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Jul., 2022.

[J136] Hanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, and David Z. Pan, “ELight: Towards Efficient and Aging-Resilient Photonic In-Memory Neurocomputing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Jun., 2022.

[J135] Keren Zhu, Hao Chen, Mingjie Liu and David Z. Pan, “Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System,” IEEE Transactions on Circuits and Systems–II: Express Briefs (TCAS-II), May, 2022.

[J134] Ahmet F. Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun and Bo Liu, "An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), May, 2022.

[J133] Jiaqi Gu, Chenghao Feng, Hanqing Zhu, Ray T. Chen and David Z. Pan, “Light in AI: Toward Efficient Neurocomputing with Optical Neural Networks - A Tutorial,” IEEE Transactions on Circuits and Systems–II: Express Briefs (TCAS-II), Apr., 2022.

[J132] Kim, Ki Yong, David Z. Pan, and Ranjit Gharpurey, “A Broadband Spectrum Channelizer With PWM-LO-Based Sub-Band Gain Control,” IEEE Journal of Solid-State Circuits, 2022

[J131] Chenghao, Feng, Zhoufeng Ying, Zheng Zhao, Jiaqi Gu, David Z. Pan, and Ray T. Chen, “Towards high-speed and energy-efficient computing: A WDM-based scalable on-chip silicon integrated optical comparator,” Laser & Photonics Reviews, Jun. 2021

[J130] Ying, Zhoufeng, Chenghao Feng, Zheng Zhao, Jiaqi Gu, Richard Soref, David Z. Pan, and Ray T. Chen, “Sequential logic and pipelining in chip-based electronic-photonic digital computing,” IEEE Photonics, Journal 12, no. 6,2020 1-11

[J129] Jiaqi Gu, Zheng Zhao, Chenghao Feng, Zhoufeng Ying, Mingjie Liu, Ray T. Chen, and David Z. Pan, “Towards Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020

[J128] Ahmet F. Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun and Bo Liu, “An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2021

[J127] Hao Chen*, Mingjie Liu*, Xiyuan Tang*, Keren Zhu*, Nan Sun and David Z. Pan, "Challenges and Opportunities Toward Fully Automated Analog Layout Design," Journal of Semiconductors,, 2020 (Invited Paper) (* in alphabetic order)

[J126] Hao Chen*, Mingjie Liu*, Biying Xu*, Keren Zhu*, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun and David Z. Pan, "MAGICAL: An Open-Source Fully Automated Analog IC Layout System from Netlist to GDSII," IEEE Design & Test,, 2020 (Invited Paper) (* indicates equal contributions)

[J125] Xinquan Li, Bei Yu, Jiaojiao Ou, Jianli Chen, David Z. Pan, and Wenxin Zhu, "Graph Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP," IEEE Transactions on VLSI Systems (TVLSI),, 2018

[J124] Abhishek Mukherjee, Miguel Gandara, Biying Xu, Shaolan Li, Linxiao Shen, Xiyuan Tang, David Z. Pan, and Nan Sun, "A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time ΔΣ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO,” IEEE Solid-State Letters , 2019

[J123] Kaveh Shamsi, Meng Li, Kenneth Plaks, Saverio Fazzari, David Z. Pan, and Yier Jin, "IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview," ACM Transactions on Design Automation of Electronic Systems (TODAES),, 2019

[J122] Shaolan Li, David Z. Pan, Nan Sun, "An OTA-Less Second-Order VCO-Based CT ΔΣ Modulator Using an Inherent Passive Integrator and Capacitive Feedback," IEEE Journal of Solid-State Circuits (JSSC), , 2019

[J121] Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, and Nan Sun, “A 13.5-ENOB, 107-uW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier,” IEEE Journal of Solid-State Circuits (ISSCC invited submission), 2020

[J120] Chenghao Feng, Zhoufeng Ying, Zheng Zhao, Jiaqi Gu, David Z. Pan, and Ray T. Chen, “Wavelength-division-multiplexing (WDM)-based integrated electronic–photonic switching network (EPSN) for high-speed data processing and transportation,” Nanophotonics, 2020,

[J119] Jing Chen, Mohamed Baker Alawieh, Yibo Lin, Maolin Zhang, Jun Zhang, Yufeng Guo and David Z. Pan, “Automatic Selection of Structure Parameters ofSilicon on Insulator Lateral Power Device Using Bayesian Optimization,” IEEE Electron Device Letters , 2020

[J118] Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany and David Z. Pan, “DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020

[J117] Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Shengguo Wang, David Z. Pan, and Xuan Zeng, “A Novel and Unified Full-chip CMP Model Aware Dummy Fill Insertion Framework with SQP-Based Optimization Method,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020

[J116] Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, and Nan Sun, “An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter,” IEEE Journal of Solid-State Circuits (JSSC), 2020

[J115] Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang and David Z. Pan, “GAN-SRAF: Sub-Resolution Assist Feature Generation using Generative Adversarial Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020

[J114] Zhoufeng Ying, Chenghao Feng, Zheng Zhao, Shounak Dhar, Hamed Dalir, Jiaqi Gu, Yue Cheng, Richard Soref, David Z. Pan and Ray T. Chen, “lectronic-photonic arithmetic logic unit for high-speed computing,” Nature Communications, Vol. 11, 2154, May 2020

[J113] Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing Ren, Brucek Khailany, “ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),, 2020

[J112] Jing Chen, Mohamed Baker Alawieh, Yibo Lin, Maolin Zhang, Jun Zhang, Yufeng Guo and David Z. Pan, “Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks,” IEEE Access 8, 2020

[J111] David Z. Pan, “Report on the 38th ACM/IEEE International Conference on Computer-Aided Design (ICCAD 2019),” IEEE Design & Test,, 2020

[J110] Taehyun Kwon, Muhammad Imran, David Z. Pan, and Joon-Sung Yang, “Virtual Tile Based Flip-flop Alignment Methodology for Clock Network Power Optimization,” EEE Transactions on VLSI Systems (TVLSI),, Vol. 28, no. 5, May 2020

[J109] Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, and Nan Sun, “An Energy-Efficient Comparator with Dynamic Floating Inverter Amplifier,” IEEE Journal of Solid-State Circuits (VLSI invited submission), 2020

[J108] Mohamed Baker Alawieh, Wei Ye, Yibo Lin and David Z. Pan, “Generative Learning in VLSI Design for Manufacturability: Current Status and Future Directions,” Journal of Microelectronic Manufacturing (JOMM), 2019

[J107] Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, and Nan Sun, “A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure,” IEEE Journal of Solid-State Circuits. (CICC invited submission), 2019

[J106] Chenghao Feng, Zhoufeng Ying, Zheng Zhao, Rohan Mital, David Z. Pan, and Ray T. Chen, “Analysis of Microresonator-Based Logic Gate for High-Speed Optical Computing in Integrated Photonics,” IEEE Journal of Selected Topics in Quantum Electronics,, 2019

[J105] Ying Chen, Yibo Lin, Lisong Dong, Tianyang Gai, Rui Chen, Yajuan Su, Yayi Wei and David Z. Pan, “SoulNet: Ultrafast Optical Source Optimization Utilizing Generative Neural Networks for Advanced Lithography,” Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), 2020

[J104] Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, and David Z. Pan, “Data Efficient Lithography Modeling with Transfer Learning and Active Data Selection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019

[J102] Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, and David Z. Pan, “Semi-Supervised Hotspot Detection with Self-Paced Multi-Task Learning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , 2019.

[J101] Jing Chen, Yibo Lin, Yufeng Guo, Maolin Zhang, Mohamed B. Alawieh, and David Z. Pan, “Lithography Hotspot Detection Using a Double Inception Module Architecture,” Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), 2019.

[J100] Zhoufeng Ying, Zheng Zhao, Chenghao Feng, Rohan Mital, Shounak Dhar, David Z. Pan, Richard Soref, and Ray T. Chen, "Automated logic synthesis for electro-optic logic-based integrated optical computing," Optics Express, 26, no. 21, 2018.

[J99] David Z. Pan, "Directed self-assembly for advanced chips," Nature Electronics, Vol. 1, no. 10, pp. 530, 2018.

[J98] Shaolan Li, Qiao Bo, Miguel Gandara, David Z. Pan, and Nan Sun, A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure," IEEE Journal of Solid-State Circuits (ISSCC invited submission), 2018.

[J97] Xingquan Li, Bei Yu, Jiaojiao Ou, Jianli Chen, David Z. Pan and Wenxing Zhu, "Graph Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP," IEEE Transactions on VLSI Systems (TVLSI), 2018.

[J96] Kaveh Shamsi, Meng Li, David Z. Pan, and Yier Jin, "On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes," IEEE Transactions on Information Forensics & Security (TIFS), Vol. 14, no. 2, pp. 347-359, 2019.

[J95] Hao Zhou, Hengliang Zhu, Tao Cui, David Z. Pan, Dian Zhou, and Xuan Zeng, "An Improved Domain Decomposition Method for Drop Impact Reliability Analysis of 3D ICs," IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), 2018.

[J94] Zhoufeng Ying, Shounak Dhar, Zheng Zhao, David Z. Pan, Richard Soref, and Ray T. Chen, "Electro-Optic Ripple-Carry Adder in Integrated Silicon Photonics for Optical Computing," Journal of Selected Topics in Quantum Electronics (JSTQE), 2018.

[J93] Hao Zhou, Hengliang Zhu, Tao Cui, David Z. Pan, Dian Zhou, and Xuan Zeng, "Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method," IEEE Transactions on VLSI Systems (TVLSI), Vol. 26, No. 7, pp. 1312-1325, July 2018.

[J92] Derong Liu, Bei Yu, Vinicius Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, and David Z. Pan, "Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.

[J91] Jun Zhang, Yufeng Guo, David Z. Pan, Kemeng Yang, Xiaojuan Lian, Jiafei Yao, and Man Li, "A New Physical Insight for the 3-D-Layout-Induced Cylindrical Breakdown in Lateral Power Devices on SOI Substrate," IEEE Transactions on Electron Devices, Vol. 65, No. 5, pp. 1843-1848, May 2018.

[J90] Ye Zhang, Wenlong Lv, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, and Xuan Zeng, "Cut Redistribution and Insertion for Advanced 1D Layout Design via Network Flow Optimization," IEEE Transactions on VLSI Systems (TVLSI) , 2018.

[J89] Zhoufeng Ying, Zheng Wang, Zheng Zhao, Shounak Dhar, David Z. Pan, Richard Soref, and Ray T. Chen, "Silicon microdisk-based full adders for optical computing," Optics Letters, Vol. 43, issue 5, pp. 983-986, (2018).

[J88] Kemeng Yang, Yufeng Guo, David Z. Pan, Jun Zhang, Man Li, Yi Tong, Lin He, and Jiafei Yao, "A Novel Variation of Lateral Doping Technique in SOI LDMOS With Circular Layout," IEEE Transactions on Electron Devices (TED), Vol. 65, no. 4, pp. 1447-1452, April 2018.

[J87] Zhoufeng Ying, Zheng Wang, Zheng Zhao, Shounak Dhar, David Z. Pan, Richard Soref, and Ray T. Chen, "Comparison of microrings and microdisks for high-speed optical modulation in silicon photonic," Applied Physics Letters, 112, 111108 (2018).

[J86] Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, and David Z. Pan, "A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.

[J85] Wuxi Li, David Z. Pan, "A New Paradigm for FPGA Placement without Explicit Packing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.

[J84] Yibo Lin, Bei Yu, Meng Li and David Z. Pan, "Layout Synthesis for Topological Quantum Circuits with 1D and 2D Architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.

[J83] Wuxi Li, Yibo Lin, Meng Li, Shounak Dhar and David Z. Pan "UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine," ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017.

[J82] Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert and David Z. Pan, "MrDP: Multiple-row Detailed Placement of Heterogeneous-sized Cells for Advanced Nodes," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.

[J81] Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, and David. Z. Pan, "Provably Secure Camouflaging Strategy for IC Protection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.

[J80] Xiaoqing Xu, Yibo Lin, Meng Li, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, and David Z. Pan, "Sub-Resolution Assist Feature Generation with Supervised Data Learning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.

[J79] Hengliang Zhu, Feng Hu, Hao Zhou, Dian Zhou, Xuan Zeng, and David Z. Pan, "Interlayer Cooling Network Design for High-Performance 3D-ICs Using Channel Patterning and Pruning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.

[J78] Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Changhao Yan, Dian Zhou, and Xuan Zeng, "An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation," ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017.

[J77] Wuxi Li, Shounak Dhar, and David Z. Pan, "UTPlaceF: A Routability-Driven FPGA Placer with Physical and Congestion Aware Packing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.

[J76] Yibo Lin, Xiaoqing Xu, Bei Yu, Ross Baldick and David Z. Pan, "Triple/quadruple patterning layout decomposition via novel linear programming and iterative rounding," Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 9781, pp. 9781-9781-11, 2016.

[J75] Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, and David Z. Pan, "Stitch Aware Detailed Placement for Multiple E-Beam Lithography," Integration, the VLSI Journal, vol. 58, pp. 47-54, 2017. (Best Paper Award)

[J74] Taehee Lee, David Z. Pan, and Joon-Sung Yang, "Clock Network Optimization with Multi-bit Flip-flop Generation Considering Multi-corner Multi-mode Timing Constraint," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 1, pp. 245-256, 2018.

[J73] Derong Liu, Bei Yu, Salim Chowdhury, and David Z. Pan, "Incremental Layer Assignment for Timing Optimization," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 22, no. 4, pp. 75:1-75:25, 2017.

[J72] Derong Liu, Bei Yu, Salim Chowdhury, and David Z. Pan, "TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 1, pp. 231-244, 2018.

[J71] Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, and David Z. Pan, "Redundant Local-Loop Insertion for Unidirectional Routing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 7, pp. 1113-1125, 2017.

[J70] Yibo Lin, Bei Yu, Biying Xu, and David Z. Pan, "Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 7, pp. 1140-1152, 2017.

[J69] Yibo Lin, Bei Yu, and David Z. Pan, "High Performance Dummy Fill Insertion with Coupling and Uniformity Constraints," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 9, pp. 1532-1544, 2017.

[J68] Vinicius Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, Jose Luıs Guntzel, and Luiz C. V. dos Santos, "Incremental Layer Assignment Driven by an External Signoff Timing Engine," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 7, pp. 1126-1139, 2017.

[J67] Xiaoqing Xu and David Z. Pan, "Toward Unidirectional Routing Closure in Advanced Technology Nodes," IPSJ Transactions on System LSI Design Methodology, Vol.10, pp. 1–12, Apr. 2017. (Invited Paper)

[J66] Tetsuaki Matsunawa, Bei Yu, and David Z Pan, "Laplacian Eigenmaps and Bayesian Clustering Based Layout Pattern Sampling and Its Applications to Hotspot Detection and OPC," Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), 2016.

[J65] Tetsuaki Matsunawa, Bei Yu, and David Z Pan, "Optical Proximity Correction with Hierarchical Bayes Model," The Journal of Microlithography, Microfabrication, and Microsystems (JM3), 2016.

[J64] Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, and David. Z. Pan, "OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations under Multiple Operating Conditions," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.

[J63] Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, and David Z. Pan, "Design for Manufacturability and Reliability in Extreme-Scaling VLSI," Science China Information Sciences (SCIS), vol.59, 061406:2, June, 2016. (Invited Paper)

[J62] Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, and Xuan Zeng, "Layout Decomposition Co-optimization for Hybrid E-Beam and Multiple Patterning Lithography," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2015.

[J61] Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, and David Z. Pan, "PARR: Pin Access Planning and Regular Routing for Self-Aligned Double Patterning," ACM Transactions on Design Automation of Electronic Systems (TODAES), 2015.

[J60] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu and David Z. Pan, "A Systematic Framework for Evaluating Standard Cell Middle-Of-Line (MOL) Robustness for Multiple Patterning Lithography," Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), 2015.

[J59] Subhendu Roy, Mihir Choudhury, Ruchir Puri and David Z. Pan, "Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2015.

[J58] Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, and Xuan Zeng, "Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography," ACM Transactions on Design Automation of Electronic Systems, 2015.

[J57] Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, and David Z. Pan, "Directed self-assembly cut mask assignment for unidirectional design," J. Micro/Nanolith. MEMS MOEMS. (JM3), 14(3), 031211, Aug 07, 2015.

[J56] Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles Alpert, and David Z. Pan, "Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 5, pp. 726-739, 2015.

[J55] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, and David Z. Pan, "Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 5, pp. 699-712, 2015.

[J54] Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, and David Z. Pan, "Clock Tree Resynthesis for Multi-corner Multi-mode Timing Closure," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 4, pp. 589-602, 2015.

[J53] Bei Yu, Kun Yuan, Duo Ding, and David Z. Pan, "Layout Decomposition for Triple Patterning Lithography," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 3, pp. 433-446, 2015.

[J52] Yongchan Ban and David Z. Pan, "Self-Aligned Double Patterning Layout Decomposition for 2D Random Metals for Sub-10nm Node Design," The Journal of Microlithography, Microfabrication, and Microsystems (JM3), vol. 14, no. 1, pp. 011004, Jan-Mar 2015

[J51] Bei Yu, Jhih-Rong Gao, Duo Ding, Xuan Zeng, and David Z. Pan, "Accurate Lithography Hotspot Detection based on Principal Component Analysis-Support Vector Machine Classifier with Hierarchical Data Clustering," The Journal of Microlithography, Microfabrication, and Microsystems (JM3), vol. 14, no. 1, pp. 011003, Jan-Mar 2015

[J50] Bei Yu, Subhendu Roy, Jhih-Rong Gao, and David Z. Pan, "Triple Patterning Lithography Layout Decomposition Using End-cutting," The Journal of Microlithography, Microfabrication, and Microsystems (JM3), vol. 14, no. 1, pp. 011002, Jan-Mar 2015

[J49] Jiwoo Pak, Sung Kyu Lim, and David Z. Pan, "Electromigration Study for Multi-scale Power/Ground Vias in TSV-based 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 12, Dec. 2014.

[J48] Subhendu Roy, Mihir Choudhury, Ruchir Puri, and David Z. Pan, "Toward Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 10, pp. 1517-1530, Oct. 2014.

[J47] Moongon Jung, Joydeep Mitra, David Z. Pan, and Sung Kyu Lim, "Full-Chip Mechanical Reliability Analysis and Optimization for 3D ICs," Communications of the ACM, Jan. 2014. (Research Highlights)

[J46] Runsheng Wang, Xiaobo Jiang, Tao Yu, Jiewen Fan, Jiang Chen, David Z. Pan, and Ru Huang, "Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II -- Experimental Results and Impacts on Device Variability," IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3676-3682, Nov. 2013.

[J45] David Z. Pan, Bei Yu, and Jhih-Rong Gao, "Design for Manufacturing with Emerging Nanolithography," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , 2013. (Keynote Paper)

[J44] Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Chip/Package Mechanical Stress Impact on 3D IC Reliability and Mobility Variations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , 2013.

[J43] Wooyoung Jang and David Z. Pan, "Chemical-Mechanical Polishing Aware Application-Specific 3D NoC Design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , 2013.

[J42] Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, and Sung Kyu Lim, "Impact of Mechanical Stress on the Full Chip Timing for TSV-based 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2013.

[J41] Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles Alpert, Earl E. Swartzlander Jr., and David Z. Pan, "Structure-Aware Placement Techniques for Designs with Datapath," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.

[J40] Wooyoung Jang and David Z. Pan, "A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip," ACM Transactions on Design Automation of Electronic Systems (TODAES) . 2012

[J39] Moongon Jung, Joydeep Mitra, David Z. Pan, and Sung Kyu Lim, "TSV Stress-aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012. i

[J38] Ashutosh Chakraborty and David Z. Pan, "Skew Management of NBTI Impacted Gated Clock Trees," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.

[J37] Kun Yuan, Bei Yu and David Z. Pan, "E-Beam Lithography Stencil Planning and Optimization with Overlapped Characters," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 2, pp. 167-179, Feb. 2012.

[J36] Duo Ding, J. Andres Torres, and David Z. Pan, "High Performance Lithography Hotspot Detection with Successively Refined Pattern Identifications and Machine Learning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 11, pp. 1621-1634, Nov. 2011.

[J35] Wooyoung Jang and David Z. Pan, "Application-Aware NoC Design for Efficient SDRAM Access," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2011

[J34] Wooyoung Jang and David Z. Pan, "A Voltage-Frequency Island aware Energy Optimization framework for networks-on-chip," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) , vol. 1, no. 3, pp. 420-432, September 2011.

[J33] Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, and David Z. Pan, "UNISM: Unified Scheduling and Mapping for General Networks on Chip," IEEE Transactions on VLSI Systems (TVLSI), July 2011.

[J32] Ryan A. Integlia, Lianghong Yin, Duo Ding, David Z. Pan, Douglas M. Gill, and Wei Jiang, "Parallel-coupled dual racetrack silicon micro-resonators for quadrature amplitude modulation," Optics Express, Vol. 19, Issue 16, pp. 14892-14902, 2011.

[J31] Yongchan Ban and David Z. Pan "Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2011.

[J30] Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky and David Z. Pan "An accurate sparse-matrix based framework for statistical static timing analysis," Integration, the VLSI Journal, 2011

[J29] Anand Rajaram and David Z. Pan, "Robust Chip-Level Clock Tree Synthesis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2011

[J28] Anand Rajaram and David Z. Pan, "MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 29, Issue 12, pp. 1845-1958, Dec 2010.

[J27] Yongchan Ban, Yuansheng Ma, Harry J. Levinson, and David Z. Pan, "Modeling and Characterization of Contact-Edge Roughness for Minimizing Design and Manufacturing Variations," The Journal of Microlithography, Microfabrication, and Microsystems (JM3), Nov. 2010.

[J26] Yongchan Ban, Savithri Sundareswaran and David Z. Pan, "Electrical Impact of Line-Edge Roughness on Sub-45nm Node Standard Cells," The Journal of Microlithography, Microfabrication, and Microsystems (JM3), Nov. 2010.

[J25] Wooyoung Jang and David Z. Pan, "An SDRAM-Aware Router for Networks-on-Chip," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 29, Issue 10, pp. 1572 - 1585, Oct 2010.

[J24] Ashutosh Chakraborty, Sean X. Shi and David Z. Pan, "Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 29, Issue 10, pp. 1533 - 1545, Oct 2010.

[J23] Xinyuan Dou, Xiaolong Wang, Xiaohui Lin, Duo Ding, David Z. Pan and Ray T. Chen, "Highly Flexible Polymeric Optical Waveguide for Out-of-plane Optical Interconnects," Optics Express, Vol.18, 16227-16233, July 2010.

[J22] Kun Yuan, Jae-Seok Yang and David Z. Pan, "Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),, Vol 29, Issue 2, pp. 185-196, Feb 2010

[J21] David Z. Pan, Minsik Cho, and Kun Yuan, "Manufacturability Aware Routing in Nanometer VLSI ", Foundations and Trends in Electronic Design Automation, Vol 4, No. 1, pp 1-97, Jan. 2010

[J20] Xinyuan Dou, Xiaolong Wang, Haiyu Huang, Xiaohui Lin, Duo Ding, David Z. Pan and Ray T. Chen, "Polymeric Waveguides with Embedded Micro-mirrors Formed by Metallic Hard Mold," Optics Express, Vol.18, 16227-16233, Dec 2009

[J19] Minsik Cho, Kun Yuan, Yongchan Ban, and David Z. Pan, "ELIAD: Efficient Lithography Aware Detailed Routing Algorithm with Compact and Macro Post-OPC Printability Prediction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) Vol 28, Issue 7, pp. 1006-1016, July 2009

[J18] Peng Yu and David Z. Pan, "ELIAS: An Accurate and Extensible Lithography Aerial Image Simulator with Improved Numerical Algorithms," IEEE Transactions on Semiconductor Manufacturing, Vol 22, No. 2, pp. 276-289, May 2009

[J17] Minsik Cho, Katrina Lu, Kun Yuan, and David Z. Pan, "BoxRouter 2.0: A Hybrid and Robust Global Router with Layer Assignment for Routability," ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol 14, Issue 2, pp. 1-21, March 2009

[J16] Peng Yu, Weifeng Qiu and David Z. Pan, "Fast Lithography Image Simulation By Exploiting Symmetries in Lithography Systems," IEEE Transactions on Semiconductor Manufacturing , Vol 21, Issue 4, pp. 638-645, Nov 2008

[J15] Tung-Chieh Chen, Minsik Cho, David Z. Pan and Yao-Wen Chang, "Metal-Density Driven Placement for CMP Variation and Routability," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , Vol 27, Issue 12, pp. 2145-2155, Dec 2008

[J14] Minsik Cho and David Z. Pan, "A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , Vol 27, Issue 10, pp. 1714-1724, Oct 2008

[J13] David Z. Pan, Peng Yu, Minsik Cho, Anand Ramalingam, Kiwoon Kim, Anand Rajaram and Sean X. Shi, "Design for Manufacturing Meets Advanced Process Control: A Survey," Journal of Process Control, Vol 18, Issue 10, pp. 975-984, Dec 2008

[J12] Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "TROY: Track Routing and Optimization for Yield," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , Vol 27, Issue 5, pp. 872-882, May 2008

[J11] M. Cho and D. Z. Pan, "Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs," IEEE Transactions on VLSI Systems, Vol 16, Issue 12, pp. 1713-1717, Dec 2008

[J10] H. Ren, D. Z. Pan, C. J. Alpert, P. Villarrubia, and G.-J. Nam, "Diffusion-Based Placement Migration with Application on Legalization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 26, Issue 12, pp. 2158-2172, December 2007

[J9] M. Cho and D. Z. Pan, "BoxRouter: A New Global Router Based on Box Expansion," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 26, Issue 12, pp. 2130-2143, December 2007

[J8] P. Yu, S. X. Shi, and D. Z. Pan,"True Process Variation Aware Optical Proximity Correction with Variational Lithography Modeling and Model Calibration," The Journal of Microlithography, Microfabrication, and Microsystems (JM3), Special Edition of Resolution Enhancement Techniques and Design for Manufacturability, September 2007

[J7] A. Ramalingam, A. Devgan, and D. Z. Pan,"Wakeup Scheduling in MTCMOS Circuits using Successive Relaxation to Minimize Ground Bounce," ASP Journal of Low Power Electronics (JOLP), Vol 3, No. 1, April 2007

[J6] H. Ren, D. Z. Pan and D. S. Kung, "Sensitivity Guided Netweighting for Placement Driven Synthesis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May, 2005.

[J5] C.-C. Chang, J. Cong, D. Z. Pan and X. Yuan,"Multilevel Global Placement with Congestion Control," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 4, pp.395-409, April 2003.

[J4] J. Cong and D. Z. Pan,"Wire Width Planning for Interconnect Performance Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 3, pp.319-329, March 2002.

[J3] J. Cong, T. Kong and D. Z. Pan,"Buffer Block Planning for Interconnect Planning and Prediction," IEEE Transactions on VLSI Systems , vol. 9, no. 6, pp.929-937, December 2001.

[J2] J. Cong, L. He, C.-K. Koh and D. Z. Pan,"Interconnect Sizing and Spacing with Consideration of Coupling Capacitance," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp.1164-1169, September 2001.

[J1] J. Cong and D. Z. Pan,"Interconnect Performance Estimation Models for Design Planning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 739--752, vol. 20, no. 6, June 2001


PATENTS (Go to Top)

[P8] Zhigang Pan and Peng Yu,"Method and System for Performing Optical Proximity Correction with Process Variations Considerations". US Patent, No. 7,711,504, Granted May 4, 2010

[P7] Minsik Cho and Zhigang Pan,"Method and Apparatus for Performing Global Routing on an Integrated Circuit Design". US Patent, No. 7,661,085, Granted on Feb. 9, 2010

[P6] Anthony Correale, Jr., David S. Kung, Douglas T. Lamb, Zhigang Pan, Ruchir Puri, David Wallach,"Multiple Voltage Integrated Circuit and Design Method Therefor". US Patent, No. 7,480,883, Granted on Jan. 20, 2009.

[P5] Anthony Correale, Jr., Rajeev Joshi, David S. Kung, Zhigang Pan, Ruchir Puri,"Single Supply Level Converter". US Patent, No. 7,119,578. Granted on Oct. 10, 2006.

[P4] Anthony Correale, Jr., David S. Kung, Douglas T. Lamb, Zhigang Pan, Ruchir Puri, David Wallach,"Multiple Voltage Integrated Circuit and Design Method Therefor", US Patent, No. 7,111,266, Granted on Sept. 19, 2006.

[P3] Anthony Correale, Jr., David S. Kung, Zhigang Pan, Ruchir Puri,"Method and Program Product of Level Converter Optimization", U.S. Patent, No. 7,089,510, Granted on August 8, 2006.

[P2] Jason Cong, Zhigang Pan, and P.V. Srinivas,"Method and Apparatus for Calculation of Crosstalk Noise in Integrated Circuits", U.S. Patent, No. 7,013,253. Granted March 2006.

[P1] Jason Cong and Zhigang Pan,"Wire Width Planning and Performance Optimization for VLSI Interconnects, U.S. Patent No. 6,408,427, Granted June 2002


 

 

 

 

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